Lines Matching +full:0 +full:x10212000
25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
75 #clock-cells = <0>;
82 #clock-cells = <0>;
92 thermal-sensors = <&thermal 0>;
96 threshold: trip-point@0 {
108 cpu_crit: cpu_crit@0 {
128 reg = <0 0x10000000 0 0x1000>;
134 reg = <0 0x10001000 0 0x1000>;
141 reg = <0 0x10003000 0 0x1000>;
148 reg = <0 0x10005000 0 0x1000>;
154 reg = <0 0x10006000 0 0x1000>;
165 reg = <0 0x10007000 0 0x100>;
171 reg = <0 0x10008000 0 0x80>;
179 reg = <0 0x1000b000 0 0x1000>;
191 reg = <0 0x1000c000 0 0x1000>;
205 reg = <0 0x10200100 0 0x1c>;
214 reg = <0 0x10204000 0 0x400>;
220 reg = <0 0x10205000 0 0x1000>;
230 reg = <0 0x10209000 0 0x1000>;
239 reg = <0 0x10211000 0 0x1000>,
240 <0 0x10212000 0 0x2000>,
241 <0 0x10214000 0 0x2000>,
242 <0 0x10216000 0 0x2000>;
247 reg = <0 0x11001000 0 0x1000>;
257 reg = <0 0x11002000 0 0x400>;
267 reg = <0 0x11003000 0 0x400>;
277 reg = <0 0x11004000 0 0x400>;
287 reg = <0 0x11005000 0 0x400>;
297 reg = <0 0x11007000 0 0x70>,
298 <0 0x11000200 0 0x80>;
304 #size-cells = <0>;
311 reg = <0 0x11008000 0 0x70>,
312 <0 0x11000280 0 0x80>;
318 #size-cells = <0>;
325 reg = <0 0x11009000 0 0x70>,
326 <0 0x11000300 0 0x80>;
332 #size-cells = <0>;
339 #size-cells = <0>;
340 reg = <0 0x1100a000 0 0x100>;
350 #thermal-sensor-cells = <0>;
352 reg = <0 0x1100b000 0 0x1000>;
364 reg = <0 0x1100d000 0 0x1000>;
372 #size-cells = <0>;
377 reg = <0 0x1100e000 0 0x1000>;
387 reg = <0 0x11014000 0 0xe0>;
392 #size-cells = <0>;
399 #size-cells = <0>;
400 reg = <0 0x11016000 0 0x100>;
412 #size-cells = <0>;
413 reg = <0 0x11017000 0 0x1000>;
424 reg = <0 0x11220000 0 0x2000>;
510 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
516 reg = <0 0x14000000 0 0x1000>;
522 reg = <0 0x1400a000 0 0x1000>;
531 reg = <0 0x14010000 0 0x1000>;
533 mediatek,larb-id = <0>;
542 reg = <0 0x15000000 0 0x1000>;
548 reg = <0 0x15001000 0 0x1000>;
559 reg = <0 0x15004000 0 0x1000>;
573 reg = <0 0x1500a000 0 0x1000>;
584 reg = <0 0x16000000 0 0x1000>;
590 reg = <0 0x16010000 0 0x1000>;
601 reg = <0 0x1a000000 0 0x1000>;
608 reg = <0 0x1a1c0000 0 0x1000>,
609 <0 0x1a1c4700 0 0x0100>;
623 reg = <0 0x1a1c4000 0 0x0700>;
630 reg = <0 0x1a1c4800 0 0x0100>;
638 reg = <0 0x1a1c4900 0 0x0700>;
648 reg = <0 0x1a240000 0 0x1000>,
649 <0 0x1a244700 0 0x0100>;
663 reg = <0 0x1a244000 0 0x0700>;
670 reg = <0 0x1a244800 0 0x0100>;
678 reg = <0 0x1a244900 0 0x0700>;
689 reg = <0 0x11200000 0 0x1000>;
705 reg = <0 0x11210000 0 0x0800>;
712 reg = <0 0x11210800 0 0x0100>;
722 reg = <0 0x1b000000 0 0x1000>;
729 reg = <0 0x1b100000 0 0x20000>;
747 #size-cells = <0>;
753 reg = <0 0x1c000000 0 0x1000>;