Lines Matching +full:mmp +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "simple-bus";
38 interrupt-parent = <&gic>;
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
48 interrupt-controller@d4282000 {
49 compatible = "marvell,mmp3-intc";
50 interrupt-controller;
51 #interrupt-cells = <1>;
54 mrvl,intc-nr-irqs = <64>;
57 pmic_mux: interrupt-controller@d4282150 {
58 compatible = "mrvl,mmp2-mux-intc";
60 interrupt-controller;
61 #interrupt-cells = <1>;
63 reg-names = "mux status", "mux mask";
64 mrvl,intc-nr-irqs = <4>;
67 rtc_mux: interrupt-controller@d4282154 {
68 compatible = "mrvl,mmp2-mux-intc";
70 interrupt-controller;
71 #interrupt-cells = <1>;
73 reg-names = "mux status", "mux mask";
74 mrvl,intc-nr-irqs = <2>;
77 hsi3_mux: interrupt-controller@d42821bc {
78 compatible = "mrvl,mmp2-mux-intc";
80 interrupt-controller;
81 #interrupt-cells = <1>;
83 reg-names = "mux status", "mux mask";
84 mrvl,intc-nr-irqs = <3>;
87 gpu_mux: interrupt-controller@d42821c0 {
88 compatible = "mrvl,mmp2-mux-intc";
90 interrupt-controller;
91 #interrupt-cells = <1>;
93 reg-names = "mux status", "mux mask";
94 mrvl,intc-nr-irqs = <3>;
97 twsi_mux: interrupt-controller@d4282158 {
98 compatible = "mrvl,mmp2-mux-intc";
100 interrupt-controller;
101 #interrupt-cells = <1>;
103 reg-names = "mux status", "mux mask";
104 mrvl,intc-nr-irqs = <5>;
107 hsi2_mux: interrupt-controller@d42821c4 {
108 compatible = "mrvl,mmp2-mux-intc";
110 interrupt-controller;
111 #interrupt-cells = <1>;
113 reg-names = "mux status", "mux mask";
114 mrvl,intc-nr-irqs = <2>;
117 dxo_mux: interrupt-controller@d42821c8 {
118 compatible = "mrvl,mmp2-mux-intc";
120 interrupt-controller;
121 #interrupt-cells = <1>;
123 reg-names = "mux status", "mux mask";
124 mrvl,intc-nr-irqs = <2>;
127 misc1_mux: interrupt-controller@d428215c {
128 compatible = "mrvl,mmp2-mux-intc";
130 interrupt-controller;
131 #interrupt-cells = <1>;
133 reg-names = "mux status", "mux mask";
134 mrvl,intc-nr-irqs = <31>;
137 ci_mux: interrupt-controller@d42821cc {
138 compatible = "mrvl,mmp2-mux-intc";
140 interrupt-controller;
141 #interrupt-cells = <1>;
143 reg-names = "mux status", "mux mask";
144 mrvl,intc-nr-irqs = <2>;
147 ssp_mux: interrupt-controller@d4282160 {
148 compatible = "mrvl,mmp2-mux-intc";
150 interrupt-controller;
151 #interrupt-cells = <1>;
153 reg-names = "mux status", "mux mask";
154 mrvl,intc-nr-irqs = <2>;
157 hsi1_mux: interrupt-controller@d4282184 {
158 compatible = "mrvl,mmp2-mux-intc";
160 interrupt-controller;
161 #interrupt-cells = <1>;
163 reg-names = "mux status", "mux mask";
164 mrvl,intc-nr-irqs = <4>;
167 misc2_mux: interrupt-controller@d4282188 {
168 compatible = "mrvl,mmp2-mux-intc";
170 interrupt-controller;
171 #interrupt-cells = <1>;
173 reg-names = "mux status", "mux mask";
174 mrvl,intc-nr-irqs = <20>;
177 hsi0_mux: interrupt-controller@d42821d0 {
178 compatible = "mrvl,mmp2-mux-intc";
180 interrupt-controller;
181 #interrupt-cells = <1>;
183 reg-names = "mux status", "mux mask";
184 mrvl,intc-nr-irqs = <5>;
187 usb_otg_phy0: usb-phy@d4207000 {
188 compatible = "marvell,mmp3-usb-phy";
190 #phy-cells = <0>;
195 compatible = "marvell,pxau2o-ehci";
199 clock-names = "USBCLK";
201 phy-names = "usb";
205 hsic_phy0: usb-phy@f0001800 {
206 compatible = "marvell,mmp3-hsic-phy";
208 #phy-cells = <0>;
213 compatible = "marvell,pxau2o-ehci";
217 clock-names = "USBCLK";
219 phy-names = "usb";
221 #address-cells = <0x01>;
222 #size-cells = <0x00>;
226 hsic_phy1: usb-phy@f0002800 {
227 compatible = "marvell,mmp3-hsic-phy";
229 #phy-cells = <0>;
234 compatible = "marvell,pxau2o-ehci";
238 clock-names = "USBCLK";
240 phy-names = "usb";
242 #address-cells = <0x01>;
243 #size-cells = <0x00>;
248 compatible = "mrvl,pxav3-mmc";
251 clock-names = "io";
257 compatible = "mrvl,pxav3-mmc";
260 clock-names = "io";
266 compatible = "mrvl,pxav3-mmc";
269 clock-names = "io";
275 compatible = "mrvl,pxav3-mmc";
278 clock-names = "io";
284 compatible = "mrvl,pxav3-mmc";
287 clock-names = "io";
288 interrupt-parent = <&hsi1_mux>;
294 compatible = "marvell,mmp2-ccic";
297 interrupt-parent = <&ci_mux>;
299 clock-names = "axi";
300 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
301 #clock-cells = <0>;
302 clock-output-names = "mclk";
307 compatible = "marvell,mmp2-ccic";
310 interrupt-parent = <&ci_mux>;
312 clock-names = "axi";
313 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
314 #clock-cells = <0>;
315 clock-output-names = "mclk";
322 interrupt-parent = <&gpu_mux>;
327 clock-names = "core", "bus";
328 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
334 interrupt-parent = <&gpu_mux>;
339 clock-names = "core", "bus";
340 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
345 compatible = "simple-bus";
346 #address-cells = <1>;
347 #size-cells = <1>;
352 compatible = "mrvl,mmp-timer";
359 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
364 reg-shift = <2>;
369 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
374 reg-shift = <2>;
379 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
384 reg-shift = <2>;
389 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
394 reg-shift = <2>;
398 gpio: gpio@d4019000 { label
399 compatible = "marvell,mmp2-gpio";
400 #address-cells = <1>;
401 #size-cells = <1>;
403 gpio-controller;
404 #gpio-cells = <2>;
406 interrupt-names = "gpio_mux";
409 interrupt-controller;
410 #interrupt-cells = <2>;
413 gcb0: gpio@d4019000 {
417 gcb1: gpio@d4019004 {
421 gcb2: gpio@d4019008 {
425 gcb3: gpio@d4019100 {
429 gcb4: gpio@d4019104 {
433 gcb5: gpio@d4019108 {
439 compatible = "mrvl,mmp-twsi";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 mrvl,i2c-fast-mode;
451 compatible = "mrvl,mmp-twsi";
453 interrupt-parent = <&twsi_mux>;
457 #address-cells = <1>;
458 #size-cells = <0>;
463 compatible = "mrvl,mmp-twsi";
465 interrupt-parent = <&twsi_mux>;
469 #address-cells = <1>;
470 #size-cells = <0>;
475 compatible = "mrvl,mmp-twsi";
477 interrupt-parent = <&twsi_mux>;
481 #address-cells = <1>;
482 #size-cells = <0>;
488 compatible = "mrvl,mmp-twsi";
490 interrupt-parent = <&twsi_mux>;
494 #address-cells = <1>;
495 #size-cells = <0>;
500 compatible = "mrvl,mmp-twsi";
502 interrupt-parent = <&twsi_mux>;
506 #address-cells = <1>;
507 #size-cells = <0>;
512 compatible = "mrvl,mmp-rtc";
515 interrupt-names = "rtc 1Hz", "rtc alarm";
516 interrupt-parent = <&rtc_mux>;
523 compatible = "marvell,mmp2-ssp";
527 #address-cells = <1>;
528 #size-cells = <0>;
533 compatible = "marvell,mmp2-ssp";
537 #address-cells = <1>;
538 #size-cells = <0>;
543 compatible = "marvell,mmp2-ssp";
547 #address-cells = <1>;
548 #size-cells = <0>;
553 compatible = "marvell,mmp2-ssp";
557 #address-cells = <1>;
558 #size-cells = <0>;
563 l2: cache-controller@d0020000 {
564 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
566 cache-unified;
567 cache-level = <2>;
571 compatible = "marvell,mmp3-clock";
575 reg-names = "mpmu", "apmu", "apbc";
576 #clock-cells = <1>;
577 #reset-cells = <1>;
578 #power-domain-cells = <1>;
581 snoop-control-unit@e0000000 {
582 compatible = "arm,arm11mp-scu";
586 gic: interrupt-controller@e0001000 {
587 compatible = "arm,arm11mp-gic";
588 interrupt-controller;
589 #interrupt-cells = <3>;
594 local-timer@e0000600 {
595 compatible = "arm,arm11mp-twd-timer";
602 compatible = "arm,arm11mp-twd-wdt";