Lines Matching +full:mmp +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
31 L2: l2-cache {
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0x3>;
37 compatible = "mrvl,axi-bus", "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
50 clock-names = "core", "bus";
51 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
54 intc: interrupt-controller@d4282000 {
55 compatible = "mrvl,mmp2-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
59 mrvl,intc-nr-irqs = <64>;
62 intcmux4: interrupt-controller@d4282150 {
63 compatible = "mrvl,mmp2-mux-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
68 reg-names = "mux status", "mux mask";
69 mrvl,intc-nr-irqs = <2>;
72 intcmux5: interrupt-controller@d4282154 {
73 compatible = "mrvl,mmp2-mux-intc";
75 interrupt-controller;
76 #interrupt-cells = <1>;
78 reg-names = "mux status", "mux mask";
79 mrvl,intc-nr-irqs = <2>;
80 mrvl,clr-mfp-irq = <1>;
83 intcmux9: interrupt-controller@d4282180 {
84 compatible = "mrvl,mmp2-mux-intc";
86 interrupt-controller;
87 #interrupt-cells = <1>;
89 reg-names = "mux status", "mux mask";
90 mrvl,intc-nr-irqs = <3>;
93 intcmux17: interrupt-controller@d4282158 {
94 compatible = "mrvl,mmp2-mux-intc";
96 interrupt-controller;
97 #interrupt-cells = <1>;
99 reg-names = "mux status", "mux mask";
100 mrvl,intc-nr-irqs = <5>;
103 intcmux35: interrupt-controller@d428215c {
104 compatible = "mrvl,mmp2-mux-intc";
106 interrupt-controller;
107 #interrupt-cells = <1>;
109 reg-names = "mux status", "mux mask";
110 mrvl,intc-nr-irqs = <15>;
113 intcmux51: interrupt-controller@d4282160 {
114 compatible = "mrvl,mmp2-mux-intc";
116 interrupt-controller;
117 #interrupt-cells = <1>;
119 reg-names = "mux status", "mux mask";
120 mrvl,intc-nr-irqs = <2>;
123 intcmux55: interrupt-controller@d4282188 {
124 compatible = "mrvl,mmp2-mux-intc";
126 interrupt-controller;
127 #interrupt-cells = <1>;
129 reg-names = "mux status", "mux mask";
130 mrvl,intc-nr-irqs = <2>;
133 usb_phy0: usb-phy@d4207000 {
134 compatible = "marvell,mmp2-usb-phy";
136 #phy-cells = <0>;
140 usb_otg0: usb-otg@d4208000 {
141 compatible = "marvell,pxau2o-ehci";
145 clock-names = "USBCLK";
147 phy-names = "usb";
152 compatible = "mrvl,pxav3-mmc";
155 clock-names = "io";
161 compatible = "mrvl,pxav3-mmc";
164 clock-names = "io";
170 compatible = "mrvl,pxav3-mmc";
173 clock-names = "io";
179 compatible = "mrvl,pxav3-mmc";
182 clock-names = "io";
188 compatible = "marvell,mmp2-ccic";
192 clock-names = "axi";
193 #clock-cells = <0>;
194 clock-output-names = "mclk";
199 compatible = "marvell,mmp2-ccic";
203 clock-names = "axi";
204 #clock-cells = <0>;
205 clock-output-names = "mclk";
209 adma0: dma-controller@d42a0800 {
210 compatible = "marvell,adma-1.0";
213 #dma-cells = <1>;
219 adma1: dma-controller@d42a0900 {
220 compatible = "marvell,adma-1.0";
223 #dma-cells = <1>;
228 compatible = "marvell,mmp2-audio-clock";
230 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
235 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
236 #clock-cells = <1>;
240 sspa0: audio-controller@d42a0c00 {
241 compatible = "marvell,mmp-sspa";
245 clock-names = "audio", "bitclk";
248 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
249 #sound-dai-cells = <0>;
253 sspa1: audio-controller@d42a0d00 {
254 compatible = "marvell,mmp-sspa";
258 clock-names = "audio", "bitclk";
261 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
262 #sound-dai-cells = <0>;
268 compatible = "mrvl,apb-bus", "simple-bus";
269 #address-cells = <1>;
270 #size-cells = <1>;
274 dma-controller@d4000000 {
275 compatible = "marvell,pdma-1.0";
279 #dma-channels = <16>;
280 dma-channels = <16>;
285 compatible = "mrvl,mmp-timer";
292 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
297 reg-shift = <2>;
302 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
307 reg-shift = <2>;
312 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
317 reg-shift = <2>;
322 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
327 reg-shift = <2>;
331 gpio: gpio@d4019000 { label
332 compatible = "marvell,mmp2-gpio";
333 #address-cells = <1>;
334 #size-cells = <1>;
336 gpio-controller;
337 #gpio-cells = <2>;
339 interrupt-names = "gpio_mux";
342 interrupt-controller;
343 #interrupt-cells = <2>;
346 gcb0: gpio@d4019000 {
350 gcb1: gpio@d4019004 {
354 gcb2: gpio@d4019008 {
358 gcb3: gpio@d4019100 {
362 gcb4: gpio@d4019104 {
366 gcb5: gpio@d4019108 {
372 compatible = "mrvl,mmp-twsi";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 mrvl,i2c-fast-mode;
384 compatible = "mrvl,mmp-twsi";
386 interrupt-parent = <&intcmux17>;
390 #address-cells = <1>;
391 #size-cells = <0>;
396 compatible = "mrvl,mmp-twsi";
398 interrupt-parent = <&intcmux17>;
402 #address-cells = <1>;
403 #size-cells = <0>;
408 compatible = "mrvl,mmp-twsi";
410 interrupt-parent = <&intcmux17>;
414 #address-cells = <1>;
415 #size-cells = <0>;
421 compatible = "mrvl,mmp-twsi";
423 interrupt-parent = <&intcmux17>;
427 #address-cells = <1>;
428 #size-cells = <0>;
433 compatible = "mrvl,mmp-twsi";
435 interrupt-parent = <&intcmux17>;
439 #address-cells = <1>;
440 #size-cells = <0>;
445 compatible = "mrvl,mmp-rtc";
448 interrupt-names = "rtc 1Hz", "rtc alarm";
449 interrupt-parent = <&intcmux5>;
456 compatible = "marvell,mmp2-ssp";
460 #address-cells = <1>;
461 #size-cells = <0>;
466 compatible = "marvell,mmp2-ssp";
470 #address-cells = <1>;
471 #size-cells = <0>;
476 compatible = "marvell,mmp2-ssp";
480 #address-cells = <1>;
481 #size-cells = <0>;
486 compatible = "marvell,mmp2-ssp";
490 #address-cells = <1>;
491 #size-cells = <0>;
497 compatible = "mmio-sram";
500 #address-cells = <1>;
501 #size-cells = <1>;
506 compatible = "marvell,mmp2-clock";
510 reg-names = "mpmu", "apmu", "apbc";
511 #clock-cells = <1>;
512 #reset-cells = <1>;
513 #power-domain-cells = <1>;