Lines Matching +full:assigned +full:- +full:addresses
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
42 clock-latency = <1000000>;
53 compatible = "marvell,armada-xp-pcie";
57 #address-cells = <3>;
58 #size-cells = <2>;
60 msi-parent = <&mpic>;
61 bus-range = <0x00 0xff>;
82 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
84 #address-cells = <3>;
85 #size-cells = <2>;
86 interrupt-names = "intx";
87 interrupts-extended = <&mpic 58>;
88 #interrupt-cells = <1>;
91 bus-range = <0x00 0xff>;
92 interrupt-map-mask = <0 0 0 7>;
93 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
97 marvell,pcie-port = <0>;
98 marvell,pcie-lane = <0>;
102 pcie1_intc: interrupt-controller {
103 interrupt-controller;
104 #interrupt-cells = <1>;
110 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
112 #address-cells = <3>;
113 #size-cells = <2>;
114 interrupt-names = "intx";
115 interrupts-extended = <&mpic 59>;
116 #interrupt-cells = <1>;
119 bus-range = <0x00 0xff>;
120 interrupt-map-mask = <0 0 0 7>;
121 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <1>;
130 pcie2_intc: interrupt-controller {
131 interrupt-controller;
132 #interrupt-cells = <1>;
138 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 interrupt-names = "intx";
143 interrupts-extended = <&mpic 60>;
144 #interrupt-cells = <1>;
147 bus-range = <0x00 0xff>;
148 interrupt-map-mask = <0 0 0 7>;
149 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
153 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <2>;
158 pcie3_intc: interrupt-controller {
159 interrupt-controller;
160 #interrupt-cells = <1>;
166 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
168 #address-cells = <3>;
169 #size-cells = <2>;
170 interrupt-names = "intx";
171 interrupts-extended = <&mpic 61>;
172 #interrupt-cells = <1>;
175 bus-range = <0x00 0xff>;
176 interrupt-map-mask = <0 0 0 7>;
177 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <3>;
186 pcie4_intc: interrupt-controller {
187 interrupt-controller;
188 #interrupt-cells = <1>;
194 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
196 #address-cells = <3>;
197 #size-cells = <2>;
198 interrupt-names = "intx";
199 interrupts-extended = <&mpic 62>;
200 #interrupt-cells = <1>;
203 bus-range = <0x00 0xff>;
204 interrupt-map-mask = <0 0 0 7>;
205 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
209 marvell,pcie-port = <1>;
210 marvell,pcie-lane = <0>;
214 pcie5_intc: interrupt-controller {
215 interrupt-controller;
216 #interrupt-cells = <1>;
221 internal-regs {
223 compatible = "marvell,armada-370-gpio",
224 "marvell,orion-gpio";
226 reg-names = "gpio", "pwm";
228 gpio-controller;
229 #gpio-cells = <2>;
230 #pwm-cells = <2>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
238 compatible = "marvell,armada-370-gpio",
239 "marvell,orion-gpio";
241 reg-names = "gpio", "pwm";
243 gpio-controller;
244 #gpio-cells = <2>;
245 #pwm-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
256 compatible = "marvell,mv78230-pinctrl";