Lines Matching +full:wr +full:- +full:hold

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4  * (DB-78460-BP)
6  * Copyright (C) 2012-2014 Marvell
9  * Gregory CLEMENT <gregory.clement@free-electrons.com>
10  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
23 /dts-v1/;
24 #include "armada-xp-mv78460.dtsi"
28 …compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
31 		stdout-path = "serial0:115200n8";
47 		devbus-bootcs {
53 			devbus,bus-width    = <16>;
54 			devbus,turn-off-ps  = <60000>;
55 			devbus,badr-skew-ps = <0>;
56 			devbus,acc-first-ps = <124000>;
57 			devbus,acc-next-ps  = <248000>;
58 			devbus,rd-setup-ps  = <0>;
59 			devbus,rd-hold-ps   = <0>;
62 			devbus,sync-enable = <0>;
63 			devbus,wr-high-ps  = <60000>;
64 			devbus,wr-low-ps   = <60000>;
65 			devbus,ale-wr-ps   = <60000>;
69 				compatible = "cfi-flash";
71 				bank-width = <2>;
75 		internal-regs {
90 				nr-ports = <2>;
97 				phy-mode = "rgmii-id";
98 				buffer-manager = <&bm>;
99 				bm,pool-long = <0>;
104 				phy-mode = "rgmii-id";
105 				buffer-manager = <&bm>;
106 				bm,pool-long = <1>;
111 				phy-mode = "sgmii";
112 				buffer-manager = <&bm>;
113 				bm,pool-long = <2>;
118 				phy-mode = "sgmii";
119 				buffer-manager = <&bm>;
120 				bm,pool-long = <3>;
128 				pinctrl-0 = <&sdio_pins>;
129 				pinctrl-names = "default";
132 				broken-cd;
147 			nand-controller@d0000 {
152 					label = "pxa3xx_nand-0";
153 					nand-rb = <0>;
154 					nand-on-flash-bbt;
157 						compatible = "fixed-partitions";
158 						#address-cells = <1>;
159 						#size-cells = <1>;
162 							label = "U-Boot";
178 		bm-bppi {
218 	phy0: ethernet-phy@0 {
222 	phy1: ethernet-phy@1 {
226 	phy2: ethernet-phy@2 {
230 	phy3: ethernet-phy@3 {
239 		#address-cells = <1>;
240 		#size-cells = <1>;
241 		compatible = "m25p64", "jedec,spi-nor";
243 		spi-max-frequency = <20000000>;