Lines Matching +full:0 +full:xf1200000
14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
43 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
44 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
45 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
55 devbus,badr-skew-ps = <0>;
58 devbus,rd-setup-ps = <0>;
59 devbus,rd-hold-ps = <0>;
62 devbus,sync-enable = <0>;
68 nor@0 {
70 reg = <0 0x1000000>;
99 bm,pool-long = <0>;
128 pinctrl-0 = <&sdio_pins>;
150 nand@0 {
151 reg = <0>;
152 label = "pxa3xx_nand-0";
153 nand-rb = <0>;
161 partition@0 {
163 reg = <0 0x800000>;
167 reg = <0x800000 0x800000>;
171 reg = <0x1000000 0x3f000000>;
191 pcie@1,0 {
192 /* Port 0, Lane 0 */
195 pcie@2,0 {
196 /* Port 0, Lane 1 */
199 pcie@3,0 {
200 /* Port 0, Lane 2 */
203 pcie@4,0 {
204 /* Port 0, Lane 3 */
207 pcie@9,0 {
208 /* Port 2, Lane 0 */
211 pcie@a,0 {
212 /* Port 3, Lane 0 */
218 phy0: ethernet-phy@0 {
219 reg = <0>;
238 flash@0 {
242 reg = <0>; /* Chip select 0 */