Lines Matching +full:0 +full:x21070
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
108 reg = <0x1400 0x500>;
113 reg = <0x8000 0x1000>;
116 arm,double-linefill-incr = <0>;
117 arm,double-linefill-wrap = <0>;
118 arm,double-linefill = <0>;
124 reg = <0xc000 0x58>;
129 reg = <0xc200 0x20>;
136 reg = <0xc600 0x20>;
144 #size-cells = <0>;
146 reg = <0xd000 0x1000>,
147 <0xc100 0x100>;
152 reg = <0x11000 0x20>;
154 #size-cells = <0>;
156 clocks = <&coreclk 0>;
162 reg = <0x11100 0x20>;
164 #size-cells = <0>;
166 clocks = <&coreclk 0>;
172 reg = <0x12000 0x100>;
176 clocks = <&coreclk 0>;
182 reg = <0x12100 0x100>;
186 clocks = <&coreclk 0>;
191 reg = <0x18000 0x20>;
193 ge0_rgmii_pins: ge-rgmii-pins-0 {
209 i2c0_pins: i2c-pins-0 {
219 ref_clk0_pins: ref-clk-pins-0 {
229 spi0_pins: spi-pins-0 {
255 uart0_pins: uart-pins-0 {
273 sata0_pins: sata-pins-0 {
309 reg = <0x18100 0x40>, <0x181c0 0x08>;
313 gpio-ranges = <&pinctrl 0 0 32>;
322 clocks = <&coreclk 0>;
328 reg = <0x18140 0x40>, <0x181c8 0x08>;
332 gpio-ranges = <&pinctrl 0 32 28>;
341 clocks = <&coreclk 0>;
347 reg = <0x18200 0x100>;
352 reg = <0x18220 0x4>;
353 clocks = <&coreclk 0>;
360 reg = <0x18300 0x100>, <0x18460 4>;
362 #size-cells = <0>;
364 comphy0: phy@0 {
365 reg = <0>;
397 reg = <0x18600 0x04>;
403 reg = <0x20000 0x100>, <0x20180 0x20>,
404 <0x20250 0x8>;
409 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
419 reg = <0x20300 0x30>, <0x21040 0x30>;
432 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
441 reg = <0x20800 0x10>;
446 reg = <0x20d20 0x6c>;
451 reg = <0x21010 0x1c>;
456 reg = <0x22000 0x1000>;
473 reg = <0x70000 0x4000>;
482 reg = <0x30000 0x4000>;
490 reg = <0x34000 0x4000>;
498 reg = <0x58000 0x500>;
506 reg = <0x60800 0x100
507 0x60a00 0x100>;
526 reg = <0x60900 0x100
527 0x60b00 0x100>;
546 #size-cells = <0>;
548 reg = <0x72004 0x4>;
554 reg = <0x90000 0x10000>;
564 marvell,crypto-sram-size = <0x800>;
569 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
576 reg = <0xa8000 0x2000>;
584 reg = <0xc8000 0xac>;
592 reg = <0xe0000 0x2000>;
600 reg = <0xe4250 0xc>;
608 reg = <0xe4078 0x4>, <0xe4070 0x8>;
614 reg = <0xd0000 0x54>;
616 #size-cells = <0>;
618 clocks = <&coredivclk 0>;
625 reg = <0xd8000 0x1000>,
626 <0xdc000 0x100>,
627 <0x18454 0x4>;
630 mrvl,clk-delay-cycles = <0x1F>;
637 reg = <0xe8000 0x4000>, <0x18410 0xc>,
638 <0x18204 0x4>;
641 clocks = <&gateclk 0>;
648 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
656 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
665 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
669 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
674 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
678 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
683 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
684 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
695 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
697 #size-cells = <0>;
698 cell-index = <0>;
700 clocks = <&coreclk 0>;
707 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
709 #size-cells = <0>;
712 clocks = <&coreclk 0>;
721 #clock-cells = <0>;
728 #clock-cells = <0>;