Lines Matching +full:sd0 +full:- +full:clk +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/gpio/gpio.h>
23 internal-regs {
27 * twice in u-boot.
45 pinctrl-0 = <&ge0_rgmii_pins>;
46 pinctrl-names = "default";
48 phy-mode = "rgmii-id";
49 buffer-manager = <&bm>;
50 bm,pool-long = <0>;
51 bm,pool-short = <1>;
60 pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
61 pinctrl-names = "default";
63 phy_dedicated: ethernet-phy@0 {
66 * register, rather than preserving reset-loaded setting.
69 marvell,reg-init = <3 16 0 0x101e>;
75 clock-frequency = <400000>;
76 pinctrl-0 = <&i2c0_pins>;
77 pinctrl-names = "default";
88 microsom_phy_clk_pins: microsom-phy-clk-pins {
89 marvell,pins = "mpp45";
93 microsom_sdhci_pins: microsom-sdhci-pins {
94 marvell,pins = "mpp21", "mpp28", "mpp37",
96 marvell,function = "sd0";
102 pinctrl-0 = <&spi1_pins>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 compatible = "w25q32", "jedec,spi-nor";
109 spi-max-frequency = <3000000>;
114 pinctrl-0 = <&uart0_pins>;
115 pinctrl-names = "default";