Lines Matching +full:0 +full:xf1200000
25 reg = <0x00000000 0x80000000>; /* 2 GB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
38 pinctrl-0 = <&i2c0_pins>;
45 pinctrl-0 = <&pca0_pins>;
52 reg = <0x20>;
64 reg = <0x21>;
69 reg = <0x57>;
80 pinctrl-0 = <&uart0_pins>;
87 pinctrl-0 = <&ge1_rgmii_pins>;
106 * The Reference Clock 0 is used to provide a
109 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
114 bm,pool-long = <0>;
121 pinctrl-0 = <&mdio_pins>;
127 phy1: ethernet-phy@0 {
128 reg = <0>;
134 pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
137 #size-cells = <0>;
139 sata0: sata-port@0 {
140 reg = <0>;
156 pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
159 #size-cells = <0>;
161 sata2: sata-port@0 {
162 reg = <0>;
174 pinctrl-0 = <&sdhci_pins>;
218 pcie@1,0 {
219 /* Port 0, Lane 0 */
227 pcie@2,0 {
228 /* Port 1, Lane 0 */
231 pcie@3,0 {
232 /* Port 2, Lane 0 */
240 gpio-fan,speed-map = < 0 0>,
248 #phy-cells = <0>;
254 #phy-cells = <0>;
268 regulator-name = "v5.0-vbus0";
278 regulator-name = "v5.0-vbus1";
297 regulator-name = "v5.0-sata0";
305 regulator-name = "v12.0-sata0";
323 regulator-name = "v5.0-sata1";
331 regulator-name = "v12.0-sata1";
347 regulator-name = "v5.0-sata2";
355 regulator-name = "v12.0-sata2";
371 regulator-name = "v5.0-sata3";
379 regulator-name = "v12.0-sata3";
395 pinctrl-0 = <&spi0_pins>;
398 flash@0 {
402 reg = <0>; /* Chip select 0 */