Lines Matching +full:0 +full:xf1200000
26 reg = <0x00000000 0x80000000>; /* 2GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
34 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
39 pinctrl-0 = <&i2c0_pins>;
54 pinctrl-0 = <&mdio_pins>;
72 pinctrl-0 = <&uart0_pins>;
82 pinctrl-0 = <&uart1_pins>;
122 * The Reference Clock 0 is used to
125 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
130 bm,pool-long = <0>;
155 pcie@1,0 {
156 /* Port 0, Lane 0 */
160 pcie@2,0 {
161 /* Port 1, Lane 0 */
165 pcie@3,0 {
166 /* Port 2, Lane 0 */
175 #phy-cells = <0>;
181 pinctrl-0 = <&xhci0_vbus_pins>;
192 pinctrl-0 = <&spi1_pins>;
195 flash@0 {
199 reg = <0>; /* Chip select 0 */
207 nand@0 {
208 reg = <0>;
209 label = "pxa3xx_nand-0";
210 nand-rb = <0>;
220 partition@0 {
222 reg = <0x00000000 0x00800000>;
228 reg = <0x00800000 0x00400000>;
234 reg = <0x00c00000 0x3f400000>;