Lines Matching +full:phy +full:- +full:reset +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
15 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
22 Pin mapping -
23 0,1 - console UART
24 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
26 4,5 - MDC/MDIO
27 6..17 - RGMII
28 18 - Topaz switch reset (active low)
29 19 - 1512 phy reset
30 20 - 1512 phy reset (eth2, optional)
31 21,28,37,38,39,40 - SD0
32 22 - USB 3.0 current limiter enable (active high)
33 24 - SFP TX fault (input active high)
34 25 - SFP present (input active low)
35 26,27 - I2C1 - connected to SFP
36 29 - Fan PWM
37 30 - CON4 mini PCIe wifi disable
38 31 - CON3 mini PCIe wifi disable
39 32 - Fuse programming power toggle (1.8v)
40 33 - CON4 mini PCIe reset
41 34 - CON2 mini PCIe wifi disable
42 35 - CON3 mini PCIe reset
43 36 - Rear button (GPIO active low)
44 41 - CON1 front panel connector
45 42 - Front LED1, or front panel CON1
46 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
47 44 - CON2 mini PCIe reset
48 45 - TPM PIRQ signal, or front panel CON1
49 46 - SFP TX disable
50 47 - Control isolation of boot sensitive SAR signals
51 48 - PSE reset
52 49 - PSE OSS signal
53 50 - PSE interrupt
54 52 - Front LED2, or front panel
55 53 - Front button
56 54 - SFP LOS (input active high)
57 55 - Fan sense
58 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
59 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
62 /dts-v1/;
63 #include <dt-bindings/input/input.h>
64 #include <dt-bindings/gpio/gpio.h>
65 #include <dt-bindings/leds/common.h>
66 #include "armada-385.dtsi"
72 /* So that mvebu u-boot can update the MAC addresses */
81 stdout-path = "serial0:115200n8";
89 reg_3p3v: regulator-3p3v {
90 compatible = "regulator-fixed";
91 regulator-name = "3P3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-always-on;
97 reg_5p0v: regulator-5p0v {
98 compatible = "regulator-fixed";
99 regulator-name = "5P0V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
105 v_usb3_con: regulator-v-usb3-con {
106 compatible = "regulator-fixed";
107 gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
110 regulator-max-microvolt = <5000000>;
111 regulator-min-microvolt = <5000000>;
112 regulator-name = "v_usb3_con";
113 vin-supply = <®_5p0v>;
114 regulator-boot-on;
115 regulator-always-on;
125 internal-regs {
132 pinctrl-0 = <&i2c0_pins>;
133 pinctrl-names = "default";
138 pinctrl-0 = <&cf_gtr_i2c1_pins>;
139 pinctrl-names = "default";
144 cf_gtr_fan_pwm: cf-gtr-fan-pwm {
146 marvell,function = "gpio";
149 cf_gtr_front_button_pins: cf-gtr-front-button-pins {
151 marvell,function = "gpio";
154 cf_gtr_i2c1_pins: i2c1-pins {
160 cf_gtr_isolation_pins: cf-gtr-isolation-pins {
162 marvell,function = "gpio";
165 cf_gtr_led_pins: led-pins {
167 marvell,function = "gpio";
170 cf_gtr_lte_disable_pins: lte-disable-pins {
172 marvell,function = "gpio";
175 cf_gtr_pci_pins: pci-pins {
176 // pci reset
178 marvell,function = "gpio";
181 cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
183 marvell,function = "gpio";
186 cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
188 marvell,function = "gpio";
191 cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
198 cf_gtr_sfp0_pins: sfp0-pins {
201 marvell,function = "gpio";
204 cf_gtr_sfp1_pins: sfp1-pins {
207 marvell,function = "gpio";
210 cf_gtr_spi1_cs_pins: spi1-cs-pins {
215 cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
217 marvell,function = "gpio";
220 cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
222 marvell,function = "gpio";
225 cf_gtr_wifi_disable_pins: wifi-disable-pins {
227 marvell,function = "gpio";
232 bus-width = <4>;
233 no-1-8-v;
234 non-removable;
235 pinctrl-0 = <&cf_gtr_sdhci_pins>;
236 pinctrl-names = "default";
239 wp-inverted;
251 vbus-supply = <&v_usb3_con>;
257 pinctrl-0 = <&cf_gtr_pci_pins>;
258 pinctrl-names = "default";
262 * the mini-PCIe connectors on the board.
264 /* CON3 - serdes 0 */
266 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
270 /* CON4 - serdes 2 */
272 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
276 /* CON2 - serdes 4 */
278 reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
285 sfp0: sfp-0 {
287 pinctrl-0 = <&cf_gtr_sfp0_pins>;
288 pinctrl-names = "default";
289 i2c-bus = <&i2c1>;
290 mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
291 tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
294 gpio-keys {
295 compatible = "gpio-keys";
296 pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
297 pinctrl-names = "default";
299 button-0 {
302 linux,can-disable;
306 button-1 {
309 linux,can-disable;
314 gpio-leds {
315 compatible = "gpio-leds";
316 pinctrl-0 = <&cf_gtr_led_pins>;
317 pinctrl-names = "default";
343 pinctrl-0 = <&ge0_rgmii_pins>;
344 pinctrl-names = "default";
345 phy = <&phy_dedicated>;
346 phy-mode = "rgmii-id";
347 buffer-manager = <&bm>;
348 bm,pool-long = <0>;
349 bm,pool-short = <1>;
355 bm,pool-long = <2>;
356 bm,pool-short = <1>;
357 buffer-manager = <&bm>;
359 phy-mode = "2500base-x";
362 fixed-link {
364 full-duplex;
370 bm,pool-long = <3>;
371 bm,pool-short = <1>;
372 buffer-manager = <&bm>;
373 managed = "in-band-status";
375 phy-mode = "sgmii";
381 pinctrl-names = "default";
382 pinctrl-0 = <&mdio_pins>;
385 phy_dedicated: ethernet-phy@0 {
387 * Annoyingly, the marvell phy driver configures the LED
388 * register, rather than preserving reset-loaded setting.
391 marvell,reg-init = <3 16 0 0x1017>;
397 pinctrl-0 = <&uart0_pins>;
398 pinctrl-names = "default";
406 pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
407 pinctrl-names = "default";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "w25q32", "jedec,spi-nor";
415 spi-max-frequency = <3000000>;
421 pinctrl-0 = <&i2c0_pins>;
422 pinctrl-names = "default";
426 temp1: temperature-sensor@4c {
432 temp2: temperature-sensor@4d {
453 pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
454 pinctrl-names = "default";
456 wifi-disable {
457 gpio-hog;
459 output-low;
460 line-name = "wifi-disable";
465 pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
466 pinctrl-names = "default";
468 lte-disable {
469 gpio-hog;
471 output-low;
472 line-name = "lte-disable";
476 * This signal, when asserted, isolates Armada 38x sample at reset pins
477 * from control of external devices. Should be de-asserted after reset.
479 sar-isolation {
480 gpio-hog;
482 output-low;
483 line-name = "sar-isolation";
486 poe-reset {
487 gpio-hog;
489 output-low;
490 line-name = "poe-reset";