Lines Matching +full:0 +full:xf1200000
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
18 0. USB 2.0 - 0 USB pins header CON12
23 0,1 - console UART
86 reg = <0x00000000 0x10000000>; /* 256 MB */
109 pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
119 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
120 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
121 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
122 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
123 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
132 pinctrl-0 = <&i2c0_pins>;
138 pinctrl-0 = <&cf_gtr_i2c1_pins>;
235 pinctrl-0 = <&cf_gtr_sdhci_pins>;
257 pinctrl-0 = <&cf_gtr_pci_pins>;
264 /* CON3 - serdes 0 */
265 pcie@1,0 {
271 pcie@2,0 {
277 pcie@3,0 {
285 sfp0: sfp-0 {
287 pinctrl-0 = <&cf_gtr_sfp0_pins>;
296 pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
299 button-0 {
316 pinctrl-0 = <&cf_gtr_led_pins>;
343 pinctrl-0 = <&ge0_rgmii_pins>;
348 bm,pool-long = <0>;
382 pinctrl-0 = <&mdio_pins>;
385 phy_dedicated: ethernet-phy@0 {
391 marvell,reg-init = <3 16 0 0x1017>;
392 reg = <0>;
397 pinctrl-0 = <&uart0_pins>;
406 pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
410 flash@0 {
412 #size-cells = <0>;
414 reg = <0>; /* Chip select 0 */
421 pinctrl-0 = <&i2c0_pins>;
428 reg = <0x4c>;
434 reg = <0x4d>;
440 reg = <0x53>;
453 pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
465 pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;