Lines Matching +full:mv88e6xxx +full:- +full:mdio +full:- +full:external
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 /dts-v1/;
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
14 /* So that mvebu u-boot can update the MAC addresses */
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-0 = <&front_button_pins>;
25 pinctrl-names = "default";
27 key-factory-default {
46 internal-regs {
50 * twice in u-boot.
60 bm,pool-long = <0>;
61 bm,pool-short = <1>;
62 buffer-manager = <&bm>;
63 phy-mode = "rgmii-id";
64 pinctrl-0 = <&ge0_rgmii_pins>;
65 pinctrl-names = "default";
68 fixed-link {
69 full-duplex;
75 &mdio {
76 pinctrl-names = "default";
77 pinctrl-0 = <&mdio_pins>;
80 ethernet-switch@0 {
82 #interrupt-cells = <2>;
83 interrupt-controller;
84 interrupt-parent = <&gpio1>;
86 pinctrl-0 = <&switch_interrupt_pins>;
87 pinctrl-names = "default";
90 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
94 switch0phy1: ethernet-phy@1 {
98 switch0phy2: ethernet-phy@2 {
102 switch0phy3: ethernet-phy@3 {
106 switch0phy4: ethernet-phy@4 {
110 switch0phy5: ethernet-phy@5 {
114 switch0phy6: ethernet-phy@6 {
118 switch0phy7: ethernet-phy@7 {
122 switch0phy8: ethernet-phy@8 {
127 mdio-external {
128 compatible = "marvell,mv88e6xxx-mdio-external";
129 #address-cells = <1>;
130 #size-cells = <0>;
132 phy1: ethernet-phy@b {
134 compatible = "ethernet-phy-ieee802.3-c45";
137 phy2: ethernet-phy@c {
139 compatible = "ethernet-phy-ieee802.3-c45";
143 ethernet-ports {
144 #address-cells = <1>;
145 #size-cells = <0>;
147 ethernet-port@0 {
149 phy-mode = "rgmii";
152 fixed-link {
153 full-duplex;
159 ethernet-port@1 {
161 phy-handle = <&switch0phy1>;
165 ethernet-port@2 {
167 phy-handle = <&switch0phy2>;
171 ethernet-port@3 {
173 phy-handle = <&switch0phy3>;
177 ethernet-port@4 {
179 phy-handle = <&switch0phy4>;
183 ethernet-port@5 {
185 phy-handle = <&switch0phy5>;
189 ethernet-port@6 {
191 phy-handle = <&switch0phy6>;
195 ethernet-port@7 {
197 phy-handle = <&switch0phy7>;
201 ethernet-port@8 {
203 phy-handle = <&switch0phy8>;
207 ethernet-port@9 {
208 /* 88X3310P external phy */
210 phy-handle = <&phy1>;
211 phy-mode = "xaui";
215 ethernet-port@a {
216 /* 88X3310P external phy */
218 phy-handle = <&phy2>;
219 phy-mode = "xaui";
227 front_button_pins: front-button-pins {
232 switch_interrupt_pins: switch-interrupt-pins {
239 pinctrl-0 = <&spi0_pins>;
240 pinctrl-names = "default";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 compatible = "jedec,spi-nor";
248 spi-max-frequency = <3000000>;
251 compatible = "fixed-partitions";
252 #address-cells = <1>;
253 #size-cells = <1>;
257 read-only;
290 pinctrl-0 = <&uart0_pins>;
291 pinctrl-names = "default";