Lines Matching +full:0 +full:xf1200000
24 pinctrl-0 = <&front_button_pins>;
36 reg = <0x00000000 0x08000000>; /* 128 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
60 bm,pool-long = <0>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
77 pinctrl-0 = <&mdio_pins>;
80 ethernet-switch@0 {
86 pinctrl-0 = <&switch_interrupt_pins>;
88 reg = <0>;
92 #size-cells = <0>;
95 reg = <0x1>;
99 reg = <0x2>;
103 reg = <0x3>;
107 reg = <0x4>;
111 reg = <0x5>;
115 reg = <0x6>;
119 reg = <0x7>;
123 reg = <0x8>;
130 #size-cells = <0>;
133 reg = <0xb>;
138 reg = <0xc>;
145 #size-cells = <0>;
147 ethernet-port@0 {
150 reg = <0>;
220 reg = <0xa>;
239 pinctrl-0 = <&spi0_pins>;
243 flash@0 {
247 reg = <0>; /* Chip select 0 */
255 partition@0 {
258 reg = <0x00000000 0x00100000>;
263 reg = <0x00100000 0x00010000>;
268 reg = <0x00110000 0x00010000>;
273 reg = <0x00120000 0x00900000>;
278 reg = <0x00a20000 0x00300000>;
283 reg = <0x00d20000 0x002e0000>;
290 pinctrl-0 = <&uart0_pins>;