Lines Matching +full:0 +full:x22000
29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
108 reg = <0x10300 0x20>;
115 #size-cells = <0>;
117 clocks = <&coreclk 0>;
124 #size-cells = <0>;
126 clocks = <&coreclk 0>;
132 reg = <0x12000 0x100>;
136 clocks = <&coreclk 0>;
142 reg = <0x12100 0x100>;
146 clocks = <&coreclk 0>;
151 reg = <0x18000 0x38>;
156 reg = <0x18740 0xc>;
164 reg = <0x20000 0x100>, <0x20180 0x20>,
165 <0x20250 0x8>;
177 reg = <0x20200 0xb0>, <0x21010 0x1c>;
181 reg = <0x20300 0x30>, <0x21040 0x30>;
186 reg = <0x20300 0x34>, <0x20704 0x4>;
191 reg = <0x20800 0x8>;
196 reg = <0x22000 0x1000>;
201 reg = <0x50000 0x500>;
208 reg = <0x51000 0x500>;
214 reg = <0x70000 0x4000>;
222 #size-cells = <0>;
224 reg = <0x72004 0x4>;
229 reg = <0x74000 0x4000>;
237 reg = <0xa0000 0x5000>;
240 clock-names = "0", "1";
246 reg = <0xd0000 0x54>;
248 #size-cells = <0>;
250 clocks = <&coredivclk 0>;
256 reg = <0xd4000 0x200>;
268 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
269 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
270 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
271 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
272 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
273 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
274 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
275 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
276 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
278 #size-cells = <0>;
279 cell-index = <0>;
281 clocks = <&coreclk 0>;
286 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
287 <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
288 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
289 <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
290 <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
291 <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
292 <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
293 <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
294 <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
296 #size-cells = <0>;
299 clocks = <&coreclk 0>;
308 #clock-cells = <0>;