Lines Matching +full:ixp4xx +full:- +full:hss

1 // SPDX-License-Identifier: ISC
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/gpio/gpio.h>
11 		#address-cells = <1>;
12 		#size-cells = <1>;
14 		compatible = "simple-bus";
15 		interrupt-parent = <&intcon>;
18 		 * The IXP4xx expansion bus is a set of up to 7 each up to 16MB
22 			/* compatible and reg filled in by per-soc device tree */
23 			native-endian;
24 			#address-cells = <2>;
25 			#size-cells = <1>;
34 			dma-ranges = <0 0x0 0x50000000 0x01000000>,
44 		qmgr: queue-manager@60000000 {
45 			compatible = "intel,ixp4xx-ahb-queue-manager";
51 			/* compatible filled in by per-soc device tree */
56 			#address-cells = <3>;
57 			#size-cells = <2>;
59 			bus-range = <0x00 0xff>;
64 			 * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
78 			dma-ranges =
85 			compatible = "intel,xscale-uart";
88 			 * The reg-offset and reg-shift is a side effect
91 			reg-offset = <3>;
92 			reg-shift = <2>;
94 			clock-frequency = <14745600>;
95 			no-loopback-test;
99 			compatible = "intel,xscale-uart";
102 			 * The reg-offset and reg-shift is a side effect
105 			reg-offset = <3>;
106 			reg-shift = <2>;
108 			clock-frequency = <14745600>;
109 			no-loopback-test;
113 			compatible = "intel,ixp4xx-gpio";
115 			gpio-controller;
116 			#gpio-cells = <2>;
117 			interrupt-controller;
118 			#interrupt-cells = <2>;
121 		intcon: interrupt-controller@c8003000 {
129 			interrupt-controller;
130 			#interrupt-cells = <2>;
134 			compatible = "intel,ixp4xx-timer";
140 			compatible = "intel,ixp4xx-network-processing-engine";
142 			#address-cells = <1>;
143 			#size-cells = <0>;
145 			/* NPE-A contains two high-speed serial links */
146 			hss@0 {
147 				compatible = "intel,ixp4xx-hss";
149 				intel,npe-handle = <&npe 0>;
153 			hss@1 {
154 				compatible = "intel,ixp4xx-hss";
156 				intel,npe-handle = <&npe 0>;
160 			/* NPE-C contains a crypto accelerator */
162 				compatible = "intel,ixp4xx-crypto";
163 				intel,npe-handle = <&npe 2>;
164 				queue-rx = <&qmgr 30>;
165 				queue-txready = <&qmgr 29>;
171 			compatible = "intel,ixp4xx-ethernet";
175 			queue-rx = <&qmgr 3>;
176 			queue-txready = <&qmgr 20>;
177 			intel,npe-handle = <&npe 1>;
182 			compatible = "intel,ixp4xx-ethernet";
186 			queue-rx = <&qmgr 0>;
187 			queue-txready = <&qmgr 0>;
188 			intel,npe-handle = <&npe 2>;
193 			compatible = "intel,ixp4xx-ethernet";
198 			queue-rx = <&qmgr 0>;
199 			queue-txready = <&qmgr 0>;