Lines Matching +full:queue +full:- +full:txready

1 // SPDX-License-Identifier: ISC
9 /dts-v1/;
11 #include "intel-ixp42x.dtsi"
12 #include <dt-bindings/input/input.h>
17 	#address-cells = <1>;
18 	#size-cells = <1>;
28 		stdout-path = "uart1:115200n8";
39 		compatible = "gpio-leds";
40 		led-power {
43 			default-state = "on";
44 			linux,default-trigger = "heartbeat";
46 		led-wireless {
49 			default-state = "on";
51 		led-internet {
54 			default-state = "on";
56 		led-dmz {
59 			default-state = "on";
63 	/* This set-up comes from an OpenWrt patch */
65 		compatible = "spi-gpio";
66 		#address-cells = <1>;
67 		#size-cells = <0>;
69 		sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
70 		miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
71 		mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
72 		cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
73 		num-chipselects = <1>;
75 		ethernet-switch@0 {
78 			spi-max-frequency = <50000000>;
85 			ethernet-ports {
86 				#address-cells = <1>;
87 				#size-cells = <0>;
89 				ethernet-port@0 {
92 					phy-mode = "mii";
93 					phy-handle = <&phy1>;
95 				ethernet-port@1 {
98 					phy-mode = "mii";
99 					phy-handle = <&phy2>;
101 				ethernet-port@2 {
104 					phy-mode = "mii";
105 					phy-handle = <&phy3>;
107 				ethernet-port@3 {
110 					phy-mode = "mii";
111 					phy-handle = <&phy4>;
113 				ethernet-port@4 {
116 					phy-mode = "mii";
117 					fixed-link {
119 						full-duplex;
130 				compatible = "intel,ixp4xx-flash", "cfi-flash";
131 				bank-width = <2>;
133 				intel,ixp4xx-eb-write-enable = <1>;
138 					compatible = "fixed-partitions";
143 					#address-cells = <1>;
144 					#size-cells = <1>;
148 						read-only;
153 						read-only;
158 						read-write;
171 			#interrupt-cells = <1>;
172 			interrupt-map-mask = <0xf800 0 0 7>;
173 			interrupt-map =
183 		 * EthB connects to the KS8995 CPU port and faces ports 1-4
192 			queue-rx = <&qmgr 3>;
193 			queue-txready = <&qmgr 20>;
194 			phy-mode = "mii";
195 			fixed-link {
197 				full-duplex;
201 				#address-cells = <1>;
202 				#size-cells = <0>;
205 				 * LAN ports 1-4 on the KS8995 switch
209 				phy1: ethernet-phy@1 {
212 				phy2: ethernet-phy@2 {
215 				phy3: ethernet-phy@3 {
218 				phy4: ethernet-phy@4 {
221 				phy5: ethernet-phy@5 {
228 		 * EthC connects to MII-P5 on the KS8995 bypassing
233 			queue-rx = <&qmgr 4>;
234 			queue-txready = <&qmgr 21>;
235 			phy-mode = "mii";
236 			phy-handle = <&phy5>;