Lines Matching +full:gpio0 +full:- +full:mode

1 // SPDX-License-Identifier: ISC
8 /dts-v1/;
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
16 	#address-cells = <1>;
17 	#size-cells = <1>;
27 		stdout-path = "uart0:115200n8";
35 		compatible = "w1-gpio";
36 		gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
42 				compatible = "intel,ixp4xx-flash", "cfi-flash";
43 				bank-width = <2>;
55 				intel,ixp4xx-eb-t3 = <3>;
56 				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
57 				intel,ixp4xx-eb-write-enable = <1>;
60 					compatible = "redboot-fis";
61 					fis-index-block = <0x1ff>;
66 				compatible = "shared-dma-pool";
69 				no-map;
71 				intel,ixp4xx-eb-t3 = <1>;
72 				intel,ixp4xx-eb-t4 = <2>;
73 				intel,ixp4xx-eb-ahb-split-transfers = <1>;
74 				intel,ixp4xx-eb-write-enable = <1>;
75 				intel,ixp4xx-eb-byte-access = <1>;
79 				 * 8250-compatible Exar XR16L2551 2 x UART
86 				interrupt-parent = <&gpio0>;
88 				clock-frequency = <1843200>;
90 				intel,ixp4xx-eb-t3 = <3>;
91 				intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
92 				intel,ixp4xx-eb-write-enable = <1>;
93 				intel,ixp4xx-eb-byte-access = <1>;
99 				compatible = "arcom,vulcan-gpio";
102 				intel,ixp4xx-eb-write-enable = <1>;
103 				intel,ixp4xx-eb-byte-access = <1>;
109 				intel,ixp4xx-eb-write-enable = <1>;
110 				intel,ixp4xx-eb-byte-access = <1>;
123 			#interrupt-cells = <1>;
124 			interrupt-map-mask = <0xf800 0 0 7>;
125 			interrupt-map =
127 			<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
128 			<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
129 			<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
130 			<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
132 			<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
133 			<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
134 			<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
135 			<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
141 			queue-rx = <&qmgr 3>;
142 			queue-txready = <&qmgr 20>;
143 			phy-mode = "rgmii";
144 			phy-handle = <&phy0>;
147 				#address-cells = <1>;
148 				#size-cells = <0>;
150 				phy0: ethernet-phy@0 {
154 				phy1: ethernet-phy@1 {
163 			queue-rx = <&qmgr 4>;
164 			queue-txready = <&qmgr 21>;
165 			phy-mode = "rgmii";
166 			phy-handle = <&phy1>;