Lines Matching +full:pl192 +full:- +full:vic
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
26 pll: clock-0 {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <1600000000>;
32 iopclk: clock-1 {
33 compatible = "fixed-factor-clock";
34 #clock-cells = <0>;
35 clock-div = <4>;
36 clock-mult = <1>;
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
46 dma-ranges;
48 L2: cache-controller@b0040000 {
49 compatible = "arm,pl310-cache";
51 cache-unified;
52 cache-level = <2>;
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
60 dma-ranges;
62 vic0: interrupt-controller@eff0000 {
63 compatible = "arm,pl192-vic";
65 interrupt-controller;
66 #interrupt-cells = <1>;
69 vic1: interrupt-controller@80f00000 {
70 compatible = "arm,pl192-vic";
72 interrupt-controller;
73 #interrupt-cells = <1>;
80 interrupt-parent = <&vic0>;
81 clock-frequency = <1846153>;
82 reg-shift = <0>;
89 interrupt-parent = <&vic0>;
90 clock-frequency = <1846153>;
91 reg-shift = <0>;
98 interrupt-parent = <&vic0>;
99 clock-frequency = <1846153>;
100 reg-shift = <0>;
104 compatible = "hpe,gxp-ehci", "generic-ehci";
107 interrupt-parent = <&vic0>;
111 compatible = "hpe,gxp-timer";
114 interrupt-parent = <&vic0>;
116 clock-names = "iop";
120 compatible = "hpe,gxp-ohci", "generic-ohci";
123 interrupt-parent = <&vic0>;