Lines Matching +full:hip01 +full:- +full:sysctrl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon Ltd. HiP01 SoC
12 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <1>;
16 gic: interrupt-controller@1e001000 {
17 compatible = "arm,cortex-a9-gic";
18 #interrupt-cells = <3>;
19 #address-cells = <0>;
20 interrupt-controller;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <144000000>;
28 clock-output-names = "hisi:refclk144khz";
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "simple-bus";
35 interrupt-parent = <&gic>;
38 amba-bus {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "simple-bus";
45 compatible = "snps,dw-apb-uart";
48 clock-names = "baudclk", "apb_pclk";
49 reg-shift = <2>;
55 compatible = "snps,dw-apb-uart";
58 clock-names = "baudclk", "apb_pclk";
59 reg-shift = <2>;
65 compatible = "snps,dw-apb-uart";
68 clock-names = "baudclk", "apb_pclk";
69 reg-shift = <2>;
75 compatible = "snps,dw-apb-uart";
78 clock-names = "baudclk", "apb_pclk";
79 reg-shift = <2>;
85 system-controller@10000000 {
86 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
88 reboot-offset = <0x4>;
92 compatible = "arm,cortex-a9-global-timer";
99 compatible = "arm,cortex-a9-twd-timer";