Lines Matching +full:reg +full:- +full:spacing
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
27 reg = <0xffe08000 0x10000>;
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
35 calxeda,led-order = <4 0 1 2 3>;
39 compatible = "calxeda,hb-sdhci";
40 reg = <0xffe0e000 0x1000>;
48 reg = <0xfff20000 0x1000>;
51 clock-names = "apb_pclk";
55 #gpio-cells = <2>;
57 gpio-controller;
58 reg = <0xfff30000 0x1000>;
61 clock-names = "apb_pclk";
66 #gpio-cells = <2>;
68 gpio-controller;
69 reg = <0xfff31000 0x1000>;
72 clock-names = "apb_pclk";
77 #gpio-cells = <2>;
79 gpio-controller;
80 reg = <0xfff32000 0x1000>;
83 clock-names = "apb_pclk";
88 #gpio-cells = <2>;
90 gpio-controller;
91 reg = <0xfff33000 0x1000>;
94 clock-names = "apb_pclk";
100 reg = <0xfff34000 0x1000>;
103 clock-names = "apb_pclk";
108 reg = <0xfff35000 0x1000>;
111 clock-names = "apb_pclk";
116 reg = <0xfff36000 0x1000>;
119 clock-names = "uartclk", "apb_pclk";
123 compatible = "ipmi-smic";
125 reg = <0xfff3a000 0x1000>;
127 reg-size = <4>;
128 reg-spacing = <4>;
132 compatible = "calxeda,hb-sregs";
133 reg = <0xfff3c000 0x1000>;
136 #address-cells = <1>;
137 #size-cells = <0>;
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <33333000>;
146 #clock-cells = <0>;
147 compatible = "calxeda,hb-pll-clock";
149 reg = <0x108>;
153 #clock-cells = <0>;
154 compatible = "calxeda,hb-pll-clock";
156 reg = <0x100>;
160 #clock-cells = <0>;
161 compatible = "calxeda,hb-a9periph-clock";
163 reg = <0x104>;
167 #clock-cells = <0>;
168 compatible = "calxeda,hb-a9bus-clock";
170 reg = <0x104>;
174 #clock-cells = <0>;
175 compatible = "calxeda,hb-pll-clock";
177 reg = <0x10C>;
181 #clock-cells = <0>;
182 compatible = "calxeda,hb-emmc-clock";
184 reg = <0x114>;
188 #clock-cells = <0>;
189 compatible = "fixed-clock";
190 clock-frequency = <150000000>;
197 reg = <0xfff3d000 0x1000>;
200 clock-names = "apb_pclk";
204 compatible = "calxeda,hb-xgmac";
205 reg = <0xfff50000 0x1000>;
207 dma-coherent;
211 compatible = "calxeda,hb-xgmac";
212 reg = <0xfff51000 0x1000>;
214 dma-coherent;
217 combophy0: combo-phy@fff58000 {
218 compatible = "calxeda,hb-combophy";
219 #phy-cells = <1>;
220 reg = <0xfff58000 0x1000>;
224 combophy5: combo-phy@fff5d000 {
225 compatible = "calxeda,hb-combophy";
226 #phy-cells = <1>;
227 reg = <0xfff5d000 0x1000>;