Lines Matching +full:0 +full:x13000
18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
107 <0x2000 0x2000>,
108 <0x4000 0x2000>,
109 <0x6000 0x2000>;
117 ranges = <0 0xff800000 0x800000>;
121 reg = <0x480 0x10>;
126 reg = <0x4c0 0x10>;
130 /* GPIOs 0 .. 31 */
133 reg = <0x500 0x04>, <0x520 0x04>;
143 reg = <0x504 0x04>, <0x524 0x04>;
153 reg = <0x508 0x04>, <0x528 0x04>;
163 reg = <0x50c 0x04>, <0x52c 0x04>;
173 reg = <0x510 0x04>, <0x530 0x04>;
183 reg = <0x514 0x04>, <0x534 0x04>;
193 reg = <0x518 0x04>, <0x538 0x04>;
203 reg = <0x51c 0x04>, <0x53c 0x04>;
212 reg = <0xb80 0x28>;
218 #size-cells = <0>;
220 reg = <0x1000 0x600>, <0x2610 0x4>;
231 #size-cells = <0>;
233 reg = <0x1800 0x600>, <0x2000 0x10>;
237 nandcs: nand@0 {
239 reg = <0>;
245 #size-cells = <0>;
247 reg = <0x3000 0xdc>;
254 arm,primecell-periphid = <0x00041081>;
255 reg = <0x11000 0x1000>;
266 reg = <0x12000 0x1000>;
275 reg = <0x13000 0x1000>;