Lines Matching +full:scl +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
51 local_intc: interrupt-controller@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
79 dma: dma-controller@7e007000 {
80 compatible = "brcm,bcm2835-dma";
89 /* DMA lite 7 - 10 */
94 interrupt-names = "dma0",
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
116 reg-names = "pm", "asb", "rpivid_asb";
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 compatible = "brcm,bcm2711-rng200";
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00341011>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00341011>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00341011>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00341011>;
175 compatible = "brcm,bcm2835-spi";
179 #address-cells = <1>;
180 #size-cells = <0>;
185 compatible = "brcm,bcm2835-spi";
189 #address-cells = <1>;
190 #size-cells = <0>;
195 compatible = "brcm,bcm2835-spi";
199 #address-cells = <1>;
200 #size-cells = <0>;
205 compatible = "brcm,bcm2835-spi";
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
239 #address-cells = <1>;
240 #size-cells = <0>;
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "brcm,bcm2711-pixelvalve0";
262 compatible = "brcm,bcm2711-pixelvalve1";
269 compatible = "brcm,bcm2711-pixelvalve2";
276 compatible = "brcm,bcm2835-pwm";
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
281 #pwm-cells = <3>;
286 compatible = "brcm,bcm2711-pixelvalve4";
293 compatible = "brcm,bcm2711-hvs";
299 compatible = "brcm,bcm2711-pixelvalve3";
306 compatible = "brcm,bcm2711-vec";
314 compatible = "brcm,brcm2711-dvp";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
325 interrupt-controller;
326 #interrupt-cells = <1>;
330 compatible = "brcm,bcm2711-hdmi0";
340 reg-names = "hdmi",
349 clock-names = "hdmi", "bvb", "audio", "cec";
351 interrupt-parent = <&aon_intr>;
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
358 dma-names = "audio-rx";
363 compatible = "brcm,bcm2711-hdmi-i2c";
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
371 compatible = "brcm,bcm2711-hdmi1";
381 reg-names = "hdmi",
391 clock-names = "hdmi", "bvb", "audio", "cec";
393 interrupt-parent = <&aon_intr>;
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
399 dma-names = "audio-rx";
404 compatible = "brcm,bcm2711-hdmi-i2c";
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
416 * so, it'll edit the dma-ranges property below accordingly.
419 compatible = "simple-bus";
420 #address-cells = <2>;
421 #size-cells = <1>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
427 compatible = "brcm,bcm2711-emmc2";
436 compatible = "arm,cortex-a72-pmu";
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
445 compatible = "arm,armv8-timer";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
461 /* Source for d/i-cache-line-size and d/i-cache-sets
463 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
464 * Source for d/i-cache-size
470 compatible = "arm,cortex-a72";
472 enable-method = "spin-table";
473 cpu-release-addr = <0x0 0x000000d8>;
474 d-cache-size = <0x8000>;
475 d-cache-line-size = <64>;
476 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
477 i-cache-size = <0xc000>;
478 i-cache-line-size = <64>;
479 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
480 next-level-cache = <&l2>;
485 compatible = "arm,cortex-a72";
487 enable-method = "spin-table";
488 cpu-release-addr = <0x0 0x000000e0>;
489 d-cache-size = <0x8000>;
490 d-cache-line-size = <64>;
491 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
492 i-cache-size = <0xc000>;
493 i-cache-line-size = <64>;
494 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
495 next-level-cache = <&l2>;
500 compatible = "arm,cortex-a72";
502 enable-method = "spin-table";
503 cpu-release-addr = <0x0 0x000000e8>;
504 d-cache-size = <0x8000>;
505 d-cache-line-size = <64>;
506 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
507 i-cache-size = <0xc000>;
508 i-cache-line-size = <64>;
509 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
510 next-level-cache = <&l2>;
515 compatible = "arm,cortex-a72";
517 enable-method = "spin-table";
518 cpu-release-addr = <0x0 0x000000f0>;
519 d-cache-size = <0x8000>;
520 d-cache-line-size = <64>;
521 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
522 i-cache-size = <0xc000>;
523 i-cache-line-size = <64>;
524 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
525 next-level-cache = <&l2>;
528 /* Source for d/i-cache-line-size and d/i-cache-sets
530 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
531 * Source for d/i-cache-size
535 l2: l2-cache0 {
537 cache-unified;
538 cache-size = <0x100000>;
539 cache-line-size = <64>;
540 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
541 cache-level = <2>;
546 compatible = "simple-bus";
547 #address-cells = <2>;
548 #size-cells = <1>;
554 compatible = "brcm,bcm2711-pcie";
557 #address-cells = <3>;
558 #interrupt-cells = <1>;
559 #size-cells = <2>;
562 interrupt-names = "pcie", "msi";
563 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
572 msi-controller;
573 msi-parent = <&pcie0>;
582 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
584 brcm,enable-ssc;
588 compatible = "brcm,bcm2711-genet-v5";
590 #address-cells = <0x1>;
591 #size-cells = <0x1>;
597 compatible = "brcm,genet-mdio-v5";
599 reg-names = "mdio";
600 #address-cells = <0x1>;
601 #size-cells = <0x0>;
606 compatible = "brcm,bcm2711-xhci", "brcm,xhci-brcm-v2";
608 #address-cells = <1>;
609 #size-cells = <0>;
611 power-domains = <&pm BCM2835_POWER_DOMAIN_USB>;
621 compatible = "brcm,2711-v3d";
624 reg-names = "hub", "core0";
626 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
634 clock-frequency = <54000000>;
638 compatible = "brcm,bcm2711-cprman";
642 coefficients = <(-487) 410040>;
643 thermal-sensors = <&thermal>;
652 compatible = "brcm,bcm2711-dsi1";
656 compatible = "brcm,bcm2711-gpio";
662 gpio-ranges = <&gpio 0 0 58>;
664 gpclk0_gpio49: gpclk0-gpio49 {
665 pin-gpclk {
666 pins = "gpio49";
668 bias-disable;
671 gpclk1_gpio50: gpclk1-gpio50 {
672 pin-gpclk {
673 pins = "gpio50";
675 bias-disable;
678 gpclk2_gpio51: gpclk2-gpio51 {
679 pin-gpclk {
680 pins = "gpio51";
682 bias-disable;
686 i2c0_gpio46: i2c0-gpio46 {
687 pin-sda {
689 pins = "gpio46";
690 bias-pull-up;
692 pin-scl {
694 pins = "gpio47";
695 bias-disable;
698 i2c1_gpio46: i2c1-gpio46 {
699 pin-sda {
701 pins = "gpio46";
702 bias-pull-up;
704 pin-scl {
706 pins = "gpio47";
707 bias-disable;
710 i2c3_gpio2: i2c3-gpio2 {
711 pin-sda {
713 pins = "gpio2";
714 bias-pull-up;
716 pin-scl {
718 pins = "gpio3";
719 bias-disable;
722 i2c3_gpio4: i2c3-gpio4 {
723 pin-sda {
725 pins = "gpio4";
726 bias-pull-up;
728 pin-scl {
730 pins = "gpio5";
731 bias-disable;
734 i2c4_gpio6: i2c4-gpio6 {
735 pin-sda {
737 pins = "gpio6";
738 bias-pull-up;
740 pin-scl {
742 pins = "gpio7";
743 bias-disable;
746 i2c4_gpio8: i2c4-gpio8 {
747 pin-sda {
749 pins = "gpio8";
750 bias-pull-up;
752 pin-scl {
754 pins = "gpio9";
755 bias-disable;
758 i2c5_gpio10: i2c5-gpio10 {
759 pin-sda {
761 pins = "gpio10";
762 bias-pull-up;
764 pin-scl {
766 pins = "gpio11";
767 bias-disable;
770 i2c5_gpio12: i2c5-gpio12 {
771 pin-sda {
773 pins = "gpio12";
774 bias-pull-up;
776 pin-scl {
778 pins = "gpio13";
779 bias-disable;
782 i2c6_gpio0: i2c6-gpio0 {
783 pin-sda {
785 pins = "gpio0";
786 bias-pull-up;
788 pin-scl {
790 pins = "gpio1";
791 bias-disable;
794 i2c6_gpio22: i2c6-gpio22 {
795 pin-sda {
797 pins = "gpio22";
798 bias-pull-up;
800 pin-scl {
802 pins = "gpio23";
803 bias-disable;
806 i2c_slave_gpio8: i2c-slave-gpio8 {
807 pins-i2c-slave {
808 pins = "gpio8",
816 jtag_gpio48: jtag-gpio48 {
817 pins-jtag {
818 pins = "gpio48",
828 mii_gpio28: mii-gpio28 {
829 pins-mii {
830 pins = "gpio28",
837 mii_gpio36: mii-gpio36 {
838 pins-mii {
839 pins = "gpio36",
847 pcm_gpio50: pcm-gpio50 {
848 pins-pcm {
849 pins = "gpio50",
857 pwm0_0_gpio12: pwm0-0-gpio12 {
858 pin-pwm {
859 pins = "gpio12";
861 bias-disable;
864 pwm0_0_gpio18: pwm0-0-gpio18 {
865 pin-pwm {
866 pins = "gpio18";
868 bias-disable;
871 pwm1_0_gpio40: pwm1-0-gpio40 {
872 pin-pwm {
873 pins = "gpio40";
875 bias-disable;
878 pwm0_1_gpio13: pwm0-1-gpio13 {
879 pin-pwm {
880 pins = "gpio13";
882 bias-disable;
885 pwm0_1_gpio19: pwm0-1-gpio19 {
886 pin-pwm {
887 pins = "gpio19";
889 bias-disable;
892 pwm1_1_gpio41: pwm1-1-gpio41 {
893 pin-pwm {
894 pins = "gpio41";
896 bias-disable;
899 pwm0_1_gpio45: pwm0-1-gpio45 {
900 pin-pwm {
901 pins = "gpio45";
903 bias-disable;
906 pwm0_0_gpio52: pwm0-0-gpio52 {
907 pin-pwm {
908 pins = "gpio52";
910 bias-disable;
913 pwm0_1_gpio53: pwm0-1-gpio53 {
914 pin-pwm {
915 pins = "gpio53";
917 bias-disable;
921 rgmii_gpio35: rgmii-gpio35 {
922 pin-start-stop {
923 pins = "gpio35";
926 pin-rx-ok {
927 pins = "gpio36";
931 rgmii_irq_gpio34: rgmii-irq-gpio34 {
932 pin-irq {
933 pins = "gpio34";
937 rgmii_irq_gpio39: rgmii-irq-gpio39 {
938 pin-irq {
939 pins = "gpio39";
943 rgmii_mdio_gpio28: rgmii-mdio-gpio28 {
944 pins-mdio {
945 pins = "gpio28",
950 rgmii_mdio_gpio37: rgmii-mdio-gpio37 {
951 pins-mdio {
952 pins = "gpio37",
958 spi0_gpio46: spi0-gpio46 {
959 pins-spi {
960 pins = "gpio46",
967 spi2_gpio46: spi2-gpio46 {
968 pins-spi {
969 pins = "gpio46",
977 spi3_gpio0: spi3-gpio0 {
978 pins-spi {
979 pins = "gpio0",
986 spi4_gpio4: spi4-gpio4 {
987 pins-spi {
988 pins = "gpio4",
995 spi5_gpio12: spi5-gpio12 {
996 pins-spi {
997 pins = "gpio12",
1004 spi6_gpio18: spi6-gpio18 {
1005 pins-spi {
1006 pins = "gpio18",
1014 uart2_gpio0: uart2-gpio0 {
1015 pin-tx {
1016 pins = "gpio0";
1018 bias-disable;
1020 pin-rx {
1021 pins = "gpio1";
1023 bias-pull-up;
1026 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 {
1027 pin-cts {
1028 pins = "gpio2";
1030 bias-pull-up;
1032 pin-rts {
1033 pins = "gpio3";
1035 bias-disable;
1038 uart3_gpio4: uart3-gpio4 {
1039 pin-tx {
1040 pins = "gpio4";
1042 bias-disable;
1044 pin-rx {
1045 pins = "gpio5";
1047 bias-pull-up;
1050 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 {
1051 pin-cts {
1052 pins = "gpio6";
1054 bias-pull-up;
1056 pin-rts {
1057 pins = "gpio7";
1059 bias-disable;
1062 uart4_gpio8: uart4-gpio8 {
1063 pin-tx {
1064 pins = "gpio8";
1066 bias-disable;
1068 pin-rx {
1069 pins = "gpio9";
1071 bias-pull-up;
1074 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 {
1075 pin-cts {
1076 pins = "gpio10";
1078 bias-pull-up;
1080 pin-rts {
1081 pins = "gpio11";
1083 bias-disable;
1086 uart5_gpio12: uart5-gpio12 {
1087 pin-tx {
1088 pins = "gpio12";
1090 bias-disable;
1092 pin-rx {
1093 pins = "gpio13";
1095 bias-pull-up;
1098 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 {
1099 pin-cts {
1100 pins = "gpio14";
1102 bias-pull-up;
1104 pin-rts {
1105 pins = "gpio15";
1107 bias-disable;
1113 #address-cells = <2>;
1130 alloc-ranges = <0x0 0x00000000 0x40000000>;
1134 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1139 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1179 arm,primecell-periphid = <0x00341011>;
1192 compatible = "brcm,bcm2711-vec";