Lines Matching +full:0 +full:x7d500000
21 #clock-cells = <0>;
28 #clock-cells = <0>;
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
53 reg = <0x40000000 0x100>;
60 reg = <0x40041000 0x1000>,
61 <0x40042000 0x2000>,
62 <0x40044000 0x2000>,
63 <0x40046000 0x2000>;
71 reg = <0x7d5d2000 0xf00>;
75 #thermal-sensor-cells = <0>;
81 reg = <0x7e007000 0xb00>;
106 brcm,dma-channel-mask = <0x07f5>;
113 reg = <0x7e100000 0x114>,
114 <0x7e00a000 0x24>,
115 <0x7ec11000 0x20>;
127 reg = <0x7e104000 0x28>;
132 reg = <0x7e201400 0x200>;
137 arm,primecell-periphid = <0x00241011>;
143 reg = <0x7e201600 0x200>;
148 arm,primecell-periphid = <0x00241011>;
154 reg = <0x7e201800 0x200>;
159 arm,primecell-periphid = <0x00241011>;
165 reg = <0x7e201a00 0x200>;
170 arm,primecell-periphid = <0x00241011>;
176 reg = <0x7e204600 0x0200>;
180 #size-cells = <0>;
186 reg = <0x7e204800 0x0200>;
190 #size-cells = <0>;
196 reg = <0x7e204a00 0x0200>;
200 #size-cells = <0>;
206 reg = <0x7e204c00 0x0200>;
210 #size-cells = <0>;
216 reg = <0x7e205600 0x200>;
220 #size-cells = <0>;
226 reg = <0x7e205800 0x200>;
230 #size-cells = <0>;
236 reg = <0x7e205a00 0x200>;
240 #size-cells = <0>;
246 reg = <0x7e205c00 0x200>;
250 #size-cells = <0>;
256 reg = <0x7e206000 0x100>;
263 reg = <0x7e207000 0x100>;
270 reg = <0x7e20a000 0x100>;
277 reg = <0x7e20c800 0x28>;
287 reg = <0x7e216000 0x100>;
294 reg = <0x7e400000 0x8000>;
300 reg = <0x7ec12000 0x100>;
307 reg = <0x7ec13000 0x1000>;
315 reg = <0x7ef00000 0x10>;
323 reg = <0x7ef00100 0x30>;
331 reg = <0x7ef00700 0x300>,
332 <0x7ef00300 0x200>,
333 <0x7ef00f00 0x80>,
334 <0x7ef00f80 0x80>,
335 <0x7ef01b00 0x200>,
336 <0x7ef01f00 0x400>,
337 <0x7ef00200 0x80>,
338 <0x7ef04300 0x100>,
339 <0x7ef20000 0x100>;
350 resets = <&dvp 0>;
352 interrupts = <0>, <1>, <2>,
364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
372 reg = <0x7ef05700 0x300>,
373 <0x7ef05300 0x200>,
374 <0x7ef05f00 0x80>,
375 <0x7ef05f80 0x80>,
376 <0x7ef06b00 0x200>,
377 <0x7ef06f00 0x400>,
378 <0x7ef00280 0x80>,
379 <0x7ef09300 0x100>,
380 <0x7ef20000 0x100>;
405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
428 reg = <0x0 0x7e340000 0x100>;
460 #size-cells = <0>;
470 cpu0: cpu@0 {
473 reg = <0>;
475 cpu-release-addr = <0x0 0x000000d8>;
476 d-cache-size = <0x8000>;
479 i-cache-size = <0xc000>;
490 cpu-release-addr = <0x0 0x000000e0>;
491 d-cache-size = <0x8000>;
494 i-cache-size = <0xc000>;
505 cpu-release-addr = <0x0 0x000000e8>;
506 d-cache-size = <0x8000>;
509 i-cache-size = <0xc000>;
520 cpu-release-addr = <0x0 0x000000f0>;
521 d-cache-size = <0x8000>;
524 i-cache-size = <0xc000>;
540 cache-size = <0x100000>;
552 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
553 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
557 reg = <0x0 0x7d500000 0x9310>;
565 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
568 <0 0 0 2 &gicv2 GIC_SPI 144
570 <0 0 0 3 &gicv2 GIC_SPI 145
572 <0 0 0 4 &gicv2 GIC_SPI 146
577 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
578 0x0 0x04000000>;
584 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
585 0x0 0xc0000000>;
591 reg = <0x0 0x7d580000 0x10000>;
592 #address-cells = <0x1>;
593 #size-cells = <0x1>;
600 reg = <0xe14 0x8>;
602 #address-cells = <0x1>;
603 #size-cells = <0x0>;
609 reg = <0x0 0x7e9c0000 0x100000>;
611 #size-cells = <0>;
623 reg = <0x0 0x7ec00000 0x4000>,
624 <0x0 0x7ec04000 0x4000>;
663 gpio-ranges = <&gpio 0 0 58>;
858 pwm0_0_gpio12: pwm0-0-gpio12 {
865 pwm0_0_gpio18: pwm0-0-gpio18 {
872 pwm1_0_gpio40: pwm1-0-gpio40 {
907 pwm0_0_gpio52: pwm0-0-gpio52 {
1131 alloc-ranges = <0x0 0x00000000 0x40000000>;