Lines Matching +full:gic +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 compatible = "arm,cortex-a9-pmu";
24 chipcommon-a-bus@18000000 {
25 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <1>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinmux_uart1>;
49 mpcore-bus@19000000 {
50 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
56 compatible = "arm,cortex-a9-scu";
60 timer@20200 {
61 compatible = "arm,cortex-a9-global-timer";
67 timer@20600 {
68 compatible = "arm,cortex-a9-twd-timer";
75 gic: interrupt-controller@21000 { label
76 compatible = "arm,cortex-a9-gic";
77 #interrupt-cells = <3>;
78 #address-cells = <0>;
79 interrupt-controller;
84 L2: cache-controller@22000 {
85 compatible = "arm,pl310-cache";
87 cache-unified;
88 arm,shared-override;
89 prefetch-data = <1>;
90 prefetch-instr = <1>;
91 cache-level = <2>;
96 compatible = "brcm,bus-axi";
99 #address-cells = <1>;
100 #size-cells = <1>;
102 #interrupt-cells = <1>;
103 interrupt-map-mask = <0x000fffff 0xffff>;
104 interrupt-map =
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
114 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
115 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
116 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
117 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
118 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
119 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
120 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
121 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
124 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
125 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
126 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
127 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
128 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
129 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
132 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
134 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
135 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
136 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
137 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
140 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
141 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
142 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
143 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
144 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
145 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
148 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
151 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
154 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
157 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
160 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
163 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
187 #address-cells = <3>;
188 #size-cells = <2>;
194 #address-cells = <3>;
195 #size-cells = <2>;
201 #address-cells = <3>;
202 #size-cells = <2>;
208 #address-cells = <1>;
209 #size-cells = <1>;
212 interrupt-parent = <&gic>;
215 compatible = "generic-ehci";
220 #address-cells = <1>;
221 #size-cells = <0>;
225 #trigger-source-cells = <0>;
230 #trigger-source-cells = <0>;
235 compatible = "generic-ohci";
239 #address-cells = <1>;
240 #size-cells = <0>;
244 #trigger-source-cells = <0>;
249 #trigger-source-cells = <0>;
257 #address-cells = <1>;
258 #size-cells = <1>;
261 interrupt-parent = <&gic>;
264 compatible = "generic-xhci";
268 phy-names = "usb";
270 #address-cells = <1>;
271 #size-cells = <0>;
275 #trigger-source-cells = <0>;
282 phy-mode = "internal";
284 fixed-link {
286 full-duplex;
292 phy-mode = "internal";
294 fixed-link {
296 full-duplex;
302 phy-mode = "internal";
304 fixed-link {
306 full-duplex;
316 compatible = "brcm,iproc-pwm";
319 #pwm-cells = <3>;
324 compatible = "brcm,iproc-mdio";
326 #size-cells = <0>;
327 #address-cells = <1>;
330 mdio-mux@18003000 {
331 compatible = "mdio-mux-mmioreg", "mdio-mux";
332 mdio-parent-bus = <&mdio>;
333 #address-cells = <1>;
334 #size-cells = <0>;
336 mux-mask = <0x200>;
340 #address-cells = <1>;
341 #size-cells = <0>;
343 usb3_phy: usb3-phy@10 {
344 compatible = "brcm,ns-ax-usb3-phy";
346 usb3-dmp-syscon = <&usb3_dmp>;
347 #phy-cells = <0>;
354 compatible = "brcm,bcm5301x-rng";
358 srab: ethernet-switch@18007000 {
359 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
365 #address-cells = <1>;
366 #size-cells = <0>;
402 fixed-link {
404 full-duplex;
415 reg-shift = <2>;
419 dmu-bus@1800c000 {
420 compatible = "simple-bus";
422 #address-cells = <1>;
423 #size-cells = <1>;
425 cru-bus@100 {
426 compatible = "brcm,ns-cru", "simple-mfd";
429 #address-cells = <1>;
430 #size-cells = <1>;
433 compatible = "brcm,ns-usb2-phy";
435 brcm,syscon-clkset = <&cru_clkset>;
437 clock-names = "phy-ref-clk";
438 #phy-cells = <0>;
442 compatible = "brcm,cru-clkset", "syscon";
447 compatible = "brcm,bcm4708-pinmux";
449 reg-names = "cru_gpio_control";
451 spi-pins {
456 pinmux_i2c: i2c-pins {
461 pinmux_pwm: pwm-pins {
467 pinmux_uart1: uart1-pins {
474 compatible = "brcm,ns-thermal";
476 #thermal-sensor-cells = <0>;
481 nand_controller: nand-controller@18028000 {
482 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
484 reg-names = "nand", "iproc-idm", "iproc-ext";
487 #address-cells = <1>;
488 #size-cells = <0>;
490 brcm,nand-has-wp;
497 thermal-zones {
498 cpu_thermal: cpu-thermal {
499 polling-delay-passive = <0>;
500 polling-delay = <1000>;
501 coefficients = <(-556) 418000>;
502 thermal-sensors = <&thermal>;
505 cpu-crit {
512 cooling-maps {