Lines Matching +full:3 +full:- +full:axis
2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "axis,artpec6";
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
61 next-level-cache = <&pl310>;
66 compatible = "arm,cortex-a9";
68 next-level-cache = <&pl310>;
73 compatible = "axis,artpec6-syscon", "syscon";
78 compatible = "arm,psci-0.2", "arm,psci";
86 compatible = "arm,cortex-a9-scu";
92 #clock-cells = <0>;
93 compatible = "fixed-clock";
94 clock-frequency = <50000000>;
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
100 clock-frequency = <125000000>;
104 #clock-cells = <1>;
105 compatible = "axis,artpec6-clkctrl";
108 clock-names = "sys_refclk";
112 compatible = "arm,cortex-a9-global-timer";
119 compatible = "arm,cortex-a9-twd-timer";
126 intc: interrupt-controller@faf01000 {
127 interrupt-controller;
128 compatible = "arm,cortex-a9-gic";
129 #interrupt-cells = <3>;
133 pl310: cache-controller@faf10000 {
134 compatible = "arm,pl310-cache";
135 cache-unified;
136 cache-level = <2>;
139 arm,data-latency = <1 1 1>;
140 arm,tag-latency = <1 1 1>;
141 arm,filter-ranges = <0x0 0x80000000>;
142 arm,double-linefill = <1>;
143 arm,double-linefill-incr = <0>;
144 arm,double-linefill-wrap = <0>;
145 prefetch-data = <1>;
146 prefetch-instr = <1>;
147 arm,prefetch-offset = <0>;
148 arm,prefetch-drop = <1>;
152 compatible = "arm,cortex-a9-pmu";
155 interrupt-affinity = <&cpu0>, <&cpu1>;
163 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
167 reg-names = "dbi", "phy", "config";
168 #address-cells = <3>;
169 #size-cells = <2>;
173 /* non-prefetchable memory */
175 num-lanes = <2>;
176 bus-range = <0x00 0xff>;
178 interrupt-names = "msi";
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
185 axis,syscon-pcie = <&syscon>;
190 compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
195 reg-names = "dbi", "dbi2", "phy", "addr_space";
196 num-ib-windows = <6>;
197 num-ob-windows = <2>;
198 num-lanes = <2>;
199 axis,syscon-pcie = <&syscon>;
204 compatible = "axis,artpec6-pinctrl";
210 bias-pull-up;
215 bias-pull-up;
220 bias-pull-up;
225 bias-pull-up;
230 compatible = "simple-bus";
231 #address-cells = <0x1>;
232 #size-cells = <0x1>;
234 dma-ranges;
237 compatible = "axis,artpec6-crypto";
254 interrupt-names = "error",
260 #dma-cells = <2>;
261 dma-channels = <8>;
262 dma-requests = <8>;
276 interrupt-names = "error",
282 #dma-cells = <2>;
283 dma-channels = <8>;
284 dma-requests = <8>;
288 clock-names = "stmmaceth", "ptp_ref";
291 compatible = "snps,dwmac-4.10a", "snps,dwmac";
294 interrupt-names = "macirq", "eth_lpi";
297 snps,axi-config = <&stmmac_axi_setup>;
298 snps,mtl-rx-config = <&mtl_rx_setup>;
299 snps,mtl-tx-config = <&mtl_tx_setup>;
308 stmmac_axi_setup: stmmac-axi-config {
319 mtl_rx_setup: rx-queues-config {
320 snps,rx-queues-to-use = <1>;
324 mtl_tx_setup: tx-queues-config {
325 snps,tx-queues-to-use = <2>;
337 clock-names = "uart_clk", "apb_pclk";
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_uart0>;
342 dma-names = "rx", "tx";
351 clock-names = "uart_clk", "apb_pclk";
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_uart1>;
356 dma-names = "rx", "tx";
365 clock-names = "uart_clk", "apb_pclk";
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_uart2>;
370 dma-names = "rx", "tx";
379 clock-names = "uart_clk", "apb_pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_uart3>;
383 <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
384 dma-names = "rx", "tx";