Lines Matching +full:0 +full:x10000000
17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
77 #clock-cells = <0>;
85 reg = <0x08 0x04>;
86 #clock-cells = <0>;
87 lock-offset = <0x14>;
88 vco-offset = <0x08>;
95 reg = <0x1c 0x04>;
96 #clock-cells = <0>;
97 lock-offset = <0x14>;
98 vco-offset = <0x1c>;
105 reg = <0x11000000 0x100>;
106 ranges = <0x0 0x11000000 0x100>;
116 reg = <0x04 0x04>;
117 #clock-cells = <0>;
118 lock-offset = <0x1c>;
119 vco-offset = <0x04>;
126 reg = <0x04 0x04>;
127 #clock-cells = <0>;
128 lock-offset = <0x1c>;
129 vco-offset = <0x04>;
150 valid-mask = <0x003fffff>;
160 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
164 bus-range = <0x00 0xff>;
165 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
166 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
167 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
168 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
169 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
170 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
171 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
172 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
173 0x02000000 0 0x80000000 /* Core module alias memory */
174 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
175 interrupt-map-mask = <0xf800 0 0 0x7>;
178 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
179 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
180 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
181 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
183 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
184 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
185 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
186 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
188 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
189 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
190 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
191 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
193 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
194 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
195 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
196 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
208 arm,primecell-periphid = <0x00041030>;
215 arm,primecell-periphid = <0x00041010>;
222 arm,primecell-periphid = <0x00041010>;
229 arm,primecell-periphid = <0x00041050>;
236 arm,primecell-periphid = <0x00041050>;
244 * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
251 ranges = <0xc0000000 0xc0000000 0x40000000>;
256 ranges = <0x00000000 0xc0000000 0x10000000>;
257 dma-ranges = <0x00000000 0xc0000000 0x10000000>;
258 reg = <0xc0000000 0x10000000>;
264 ranges = <0x00000000 0xd0000000 0x10000000>;
265 dma-ranges = <0x00000000 0xd0000000 0x10000000>;
266 reg = <0xd0000000 0x10000000>;
272 ranges = <0x00000000 0xe0000000 0x10000000>;
273 dma-ranges = <0x00000000 0xe0000000 0x10000000>;
274 reg = <0xe0000000 0x10000000>;
280 ranges = <0x00000000 0xf0000000 0x10000000>;
281 dma-ranges = <0x00000000 0xf0000000 0x10000000>;
282 reg = <0xf0000000 0x10000000>;