Lines Matching full:clkc

7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
27 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
29 			clocks = <&clkc CLKID_CPUCLK>;
39 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
41 			clocks = <&clkc CLKID_CPUCLK>;
51 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
53 			clocks = <&clkc CLKID_CPUCLK>;
63 			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
65 			clocks = <&clkc CLKID_CPUCLK>;
231 			compatible = "amlogic,meson8b-ddr-clkc";
274 			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
284 	clocks = <&clkc CLKID_AIU_GLUE>,
285 		 <&clkc CLKID_I2S_OUT>,
286 		 <&clkc CLKID_AOCLK_GATE>,
287 		 <&clkc CLKID_CTS_AMCLK>,
288 		 <&clkc CLKID_MIXER_IFACE>,
289 		 <&clkc CLKID_IEC958>,
290 		 <&clkc CLKID_IEC958_GATE>,
291 		 <&clkc CLKID_CTS_MCLK_I958>,
292 		 <&clkc CLKID_CTS_I958>;
390 	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
410 			 <&clkc CLKID_FCLK_DIV4>,
411 			 <&clkc CLKID_FCLK_DIV3>;
555 	clocks = <&clkc CLKID_EFUSE>;
570 	clocks = <&clkc CLKID_ETH>,
571 		 <&clkc CLKID_MPLL2>,
572 		 <&clkc CLKID_MPLL2>,
573 		 <&clkc CLKID_FCLK_DIV2>;
591 	clkc: clock-controller {  label
592 		compatible = "amlogic,meson8b-clkc";
617 		clocks = <&clkc CLKID_VPU>;
619 		assigned-clocks = <&clkc CLKID_VPU>;
625 	clocks = <&clkc CLKID_RNG0>;
630 	clocks = <&clkc CLKID_CLK81>;
634 	clocks = <&clkc CLKID_I2C>;
638 	clocks = <&clkc CLKID_I2C>;
663 		clocks = <&clkc CLKID_PERIPH>;
676 		clocks = <&clkc CLKID_PERIPH>;
684 		 <&clkc CLKID_FCLK_DIV4>,
685 		 <&clkc CLKID_FCLK_DIV3>;
692 		 <&clkc CLKID_FCLK_DIV4>,
693 		 <&clkc CLKID_FCLK_DIV3>;
703 	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
713 		 <&clkc CLKID_FCLK_DIV4>,
714 		 <&clkc CLKID_FCLK_DIV3>,
715 		 <&clkc CLKID_FCLK_DIV5>,
716 		 <&clkc CLKID_SDHC>;
729 	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
734 	clocks = <&xtal>, <&clkc CLKID_CLK81>;
740 	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
746 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
752 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
758 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
764 	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
770 	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
776 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
783 	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;