Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ccu
1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
20 clock-output-names = "osc24M";
23 osc32k: clk-32k {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <32768>;
27 clock-output-names = "osc32k";
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,arm926ej-s";
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
48 sram-controller@1c00000 {
49 compatible = "allwinner,suniv-f1c100s-system-control",
50 "allwinner,sun4i-a10-system-control";
52 #address-cells = <1>;
53 #size-cells = <1>;
57 compatible = "mmio-sram";
59 #address-cells = <1>;
60 #size-cells = <1>;
63 otg_sram: sram-section@0 {
64 compatible = "allwinner,suniv-f1c100s-sram-d",
65 "allwinner,sun4i-a10-sram-d";
73 compatible = "allwinner,suniv-f1c100s-spi",
74 "allwinner,sun8i-h3-spi";
77 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
78 clock-names = "ahb", "mod";
79 resets = <&ccu RST_BUS_SPI0>;
81 num-cs = <1>;
82 #address-cells = <1>;
83 #size-cells = <0>;
87 compatible = "allwinner,suniv-f1c100s-spi",
88 "allwinner,sun8i-h3-spi";
91 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
92 clock-names = "ahb", "mod";
93 resets = <&ccu RST_BUS_SPI1>;
95 num-cs = <1>;
96 #address-cells = <1>;
97 #size-cells = <0>;
101 compatible = "allwinner,suniv-f1c100s-mmc",
102 "allwinner,sun7i-a20-mmc";
104 clocks = <&ccu CLK_BUS_MMC0>,
105 <&ccu CLK_MMC0>,
106 <&ccu CLK_MMC0_OUTPUT>,
107 <&ccu CLK_MMC0_SAMPLE>;
108 clock-names = "ahb", "mmc", "output", "sample";
109 resets = <&ccu RST_BUS_MMC0>;
110 reset-names = "ahb";
112 pinctrl-names = "default";
113 pinctrl-0 = <&mmc0_pins>;
115 #address-cells = <1>;
116 #size-cells = <0>;
120 compatible = "allwinner,suniv-f1c100s-mmc",
121 "allwinner,sun7i-a20-mmc";
123 clocks = <&ccu CLK_BUS_MMC1>,
124 <&ccu CLK_MMC1>,
125 <&ccu CLK_MMC1_OUTPUT>,
126 <&ccu CLK_MMC1_SAMPLE>;
127 clock-names = "ahb", "mmc", "output", "sample";
128 resets = <&ccu RST_BUS_MMC1>;
129 reset-names = "ahb";
132 #address-cells = <1>;
133 #size-cells = <0>;
137 compatible = "allwinner,suniv-f1c100s-musb";
139 clocks = <&ccu CLK_BUS_OTG>;
140 resets = <&ccu RST_BUS_OTG>;
142 interrupt-names = "mc";
144 phy-names = "usb";
151 compatible = "allwinner,suniv-f1c100s-usb-phy";
153 reg-names = "phy_ctrl";
154 clocks = <&ccu CLK_USB_PHY0>;
155 clock-names = "usb0_phy";
156 resets = <&ccu RST_USB_PHY0>;
157 reset-names = "usb0_reset";
158 #phy-cells = <1>;
162 ccu: clock@1c20000 { label
163 compatible = "allwinner,suniv-f1c100s-ccu";
166 clock-names = "hosc", "losc";
167 #clock-cells = <1>;
168 #reset-cells = <1>;
171 intc: interrupt-controller@1c20400 {
172 compatible = "allwinner,suniv-f1c100s-ic";
174 interrupt-controller;
175 #interrupt-cells = <1>;
179 compatible = "allwinner,suniv-f1c100s-pinctrl";
182 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
183 clock-names = "apb", "hosc", "losc";
184 gpio-controller;
185 interrupt-controller;
186 #interrupt-cells = <3>;
187 #gpio-cells = <3>;
189 mmc0_pins: mmc0-pins {
192 drive-strength = <30>;
195 /omit-if-no-ref/
196 i2c0_pd_pins: i2c0-pd-pins {
201 spi0_pc_pins: spi0-pc-pins {
206 uart0_pe_pins: uart0-pe-pins {
211 /omit-if-no-ref/
212 uart1_pa_pins: uart1-pa-pins {
219 compatible = "allwinner,suniv-f1c100s-i2c",
220 "allwinner,sun6i-a31-i2c";
223 clocks = <&ccu CLK_BUS_I2C0>;
224 resets = <&ccu RST_BUS_I2C0>;
225 #address-cells = <1>;
226 #size-cells = <0>;
231 compatible = "allwinner,suniv-f1c100s-i2c",
232 "allwinner,sun6i-a31-i2c";
235 clocks = <&ccu CLK_BUS_I2C1>;
236 resets = <&ccu RST_BUS_I2C1>;
237 #address-cells = <1>;
238 #size-cells = <0>;
243 compatible = "allwinner,suniv-f1c100s-i2c",
244 "allwinner,sun6i-a31-i2c";
247 clocks = <&ccu CLK_BUS_I2C2>;
248 resets = <&ccu RST_BUS_I2C2>;
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "allwinner,suniv-f1c100s-timer";
262 compatible = "allwinner,suniv-f1c100s-wdt",
263 "allwinner,sun6i-a31-wdt";
270 compatible = "allwinner,suniv-f1c100s-pwm",
271 "allwinner,sun7i-a20-pwm";
274 #pwm-cells = <3>;
279 compatible = "allwinner,suniv-f1c100s-ir",
280 "allwinner,sun6i-a31-ir";
282 clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
283 clock-names = "apb", "ir";
284 resets = <&ccu RST_BUS_IR>;
290 compatible = "allwinner,suniv-f1c100s-lradc",
291 "allwinner,sun8i-a83t-r-lradc";
298 compatible = "snps,dw-apb-uart";
301 reg-shift = <2>;
302 reg-io-width = <4>;
303 clocks = <&ccu CLK_BUS_UART0>;
304 resets = <&ccu RST_BUS_UART0>;
309 compatible = "snps,dw-apb-uart";
312 reg-shift = <2>;
313 reg-io-width = <4>;
314 clocks = <&ccu CLK_BUS_UART1>;
315 resets = <&ccu RST_BUS_UART1>;
320 compatible = "snps,dw-apb-uart";
323 reg-shift = <2>;
324 reg-io-width = <4>;
325 clocks = <&ccu CLK_BUS_UART2>;
326 resets = <&ccu RST_BUS_UART2>;