Lines Matching +full:0 +full:x01ee0000
64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
162 polling-delay = <0>;
176 reg = <0x01000000 0x10000>;
187 compatible = "allwinner,sun8i-r40-de2-mixer-0";
188 reg = <0x01100000 0x100000>;
197 #size-cells = <0>;
210 reg = <0x01200000 0x100000>;
219 #size-cells = <0>;
233 reg = <0x01400000 0x20000>;
252 reg = <0x01c00000 0x30>;
259 reg = <0x01d00000 0xd0000>;
262 ranges = <0 0x01d00000 0xd0000>;
264 ve_sram: sram-section@0 {
267 reg = <0x000000 0x80000>;
276 reg = <0x01c00030 0x0c>;
277 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
283 reg = <0x01c02000 0x1000>;
295 reg = <0x01c05000 0x1000>;
302 #size-cells = <0>;
308 reg = <0x01c06000 0x1000>;
315 #size-cells = <0>;
321 reg = <0x01c09000 0x1000>;
334 reg = <0x01c0e000 0x1000>;
348 reg = <0x01c0f000 0x1000>;
353 pinctrl-0 = <&mmc0_pins>;
358 #size-cells = <0>;
364 reg = <0x01c10000 0x1000>;
372 #size-cells = <0>;
378 reg = <0x01c11000 0x1000>;
383 pinctrl-0 = <&mmc2_pins>;
388 #size-cells = <0>;
394 reg = <0x01c12000 0x1000>;
399 pinctrl-0 = <&mmc3_pins>;
404 #size-cells = <0>;
409 reg = <0x01c13400 0x14>,
410 <0x01c14800 0x4>,
411 <0x01c19800 0x4>,
412 <0x01c1c800 0x4>;
435 reg = <0x01c15000 0x1000>;
445 reg = <0x01c17000 0x1000>;
452 #size-cells = <0>;
457 reg = <0x01c18000 0x1000>;
467 reg = <0x01c19000 0x100>;
478 reg = <0x01c19400 0x100>;
490 reg = <0x01c1c000 0x100>;
501 reg = <0x01c1c400 0x100>;
514 reg = <0x01c1f000 0x1000>;
521 #size-cells = <0>;
526 reg = <0x01c20000 0x400>;
535 reg = <0x01c20400 0x400>;
544 reg = <0x01c20800 0x400>;
746 reg = <0x01c20c00 0x90>;
758 reg = <0x01c20c90 0x10>;
766 reg = <0x01c21800 0x400>;
767 pinctrl-0 = <&ir0_pins>;
779 reg = <0x01c21c00 0x400>;
780 pinctrl-0 = <&ir1_pins>;
790 #sound-dai-cells = <0>;
793 reg = <0x01c22000 0x400>;
803 #sound-dai-cells = <0>;
806 reg = <0x01c22400 0x400>;
816 #sound-dai-cells = <0>;
819 reg = <0x01c22800 0x400>;
830 reg = <0x01c24c00 0x100>;
841 reg = <0x01c28000 0x400>;
852 reg = <0x01c28400 0x400>;
863 reg = <0x01c28800 0x400>;
874 reg = <0x01c28c00 0x400>;
885 reg = <0x01c29000 0x400>;
896 reg = <0x01c29400 0x400>;
907 reg = <0x01c29800 0x400>;
918 reg = <0x01c29c00 0x400>;
929 reg = <0x01c2ac00 0x400>;
933 pinctrl-0 = <&i2c0_pins>;
937 #size-cells = <0>;
942 reg = <0x01c2b000 0x400>;
946 pinctrl-0 = <&i2c1_pins>;
950 #size-cells = <0>;
955 reg = <0x01c2b400 0x400>;
959 pinctrl-0 = <&i2c2_pins>;
963 #size-cells = <0>;
968 reg = <0x01c2b800 0x400>;
972 pinctrl-0 = <&i2c3_pins>;
976 #size-cells = <0>;
981 reg = <0x01c2bc00 0x400>;
990 reg = <0x01c2c000 0x400>;
994 pinctrl-0 = <&i2c4_pins>;
998 #size-cells = <0>;
1003 reg = <0x01c40000 0x10000>;
1026 reg = <0x01c50000 0x10000>;
1038 #size-cells = <0>;
1044 reg = <0x01c62000 0x1000>;
1048 dma-ranges = <0x00000000 0x40000000 0x80000000>;
1054 reg = <0x01c70000 0x1000>;
1075 #size-cells = <0>;
1077 tcon_top_mixer0_in: port@0 {
1078 reg = <0>;
1087 #size-cells = <0>;
1090 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1091 reg = <0>;
1111 #size-cells = <0>;
1122 #size-cells = <0>;
1125 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1126 reg = <0>;
1146 #size-cells = <0>;
1149 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1150 reg = <0>;
1172 reg = <0x01c73000 0x1000>;
1182 #size-cells = <0>;
1184 tcon_tv0_in: port@0 {
1186 #size-cells = <0>;
1187 reg = <0>;
1189 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1190 reg = <0>;
1202 #size-cells = <0>;
1215 reg = <0x01c74000 0x1000>;
1225 #size-cells = <0>;
1227 tcon_tv1_in: port@0 {
1229 #size-cells = <0>;
1230 reg = <0>;
1232 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1233 reg = <0>;
1245 #size-cells = <0>;
1258 reg = <0x01c81000 0x1000>,
1259 <0x01c82000 0x2000>,
1260 <0x01c84000 0x2000>,
1261 <0x01c86000 0x2000>;
1270 reg = <0x01ee0000 0x10000>;
1284 #size-cells = <0>;
1286 hdmi_in: port@0 {
1287 reg = <0>;
1302 reg = <0x01ef0000 0x10000>;
1305 clock-names = "bus", "mod", "pll-0", "pll-1";
1308 #phy-cells = <0>;