Lines Matching +full:sun8i +full:- +full:h3 +full:- +full:ccu
4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
57 opp-816000000 {
58 opp-hz = /bits/ 64 <816000000>;
59 opp-microvolt = <1100000 1100000 1300000>;
60 clock-latency-ns = <244144>; /* 8 32k periods */
63 opp-1008000000 {
64 opp-hz = /bits/ 64 <1008000000>;
65 opp-microvolt = <1200000 1200000 1300000>;
66 clock-latency-ns = <244144>; /* 8 32k periods */
71 #address-cells = <1>;
72 #size-cells = <0>;
75 compatible = "arm,cortex-a7";
78 clocks = <&ccu CLK_CPUX>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu0_opp_table>;
81 #cooling-cells = <2>;
85 compatible = "arm,cortex-a7";
88 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu";
90 operating-points-v2 = <&cpu0_opp_table>;
91 #cooling-cells = <2>;
95 compatible = "arm,cortex-a7";
98 clocks = <&ccu CLK_CPUX>;
99 clock-names = "cpu";
100 operating-points-v2 = <&cpu0_opp_table>;
101 #cooling-cells = <2>;
105 compatible = "arm,cortex-a7";
108 clocks = <&ccu CLK_CPUX>;
109 clock-names = "cpu";
110 operating-points-v2 = <&cpu0_opp_table>;
111 #cooling-cells = <2>;
115 gpu_opp_table: opp-table-gpu {
116 compatible = "operating-points-v2";
118 opp-120000000 {
119 opp-hz = /bits/ 64 <120000000>;
122 opp-312000000 {
123 opp-hz = /bits/ 64 <312000000>;
126 opp-432000000 {
127 opp-hz = /bits/ 64 <432000000>;
130 opp-576000000 {
131 opp-hz = /bits/ 64 <576000000>;
136 compatible = "arm,cortex-a7-pmu";
141 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
145 compatible = "arm,armv7-timer";
154 compatible = "allwinner,sun8i-h3-deinterlace";
156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
157 <&ccu CLK_DEINTERLACE>,
158 <&ccu CLK_DRAM_DEINTERLACE>;
159 clock-names = "bus", "mod", "ram";
160 resets = <&ccu RST_BUS_DEINTERLACE>;
163 interconnect-names = "dma-mem";
166 syscon: system-control@1c00000 {
167 compatible = "allwinner,sun8i-h3-system-control";
169 #address-cells = <1>;
170 #size-cells = <1>;
174 compatible = "mmio-sram";
176 #address-cells = <1>;
177 #size-cells = <1>;
180 ve_sram: sram-section@0 {
181 compatible = "allwinner,sun8i-h3-sram-c1",
182 "allwinner,sun4i-a10-sram-c1";
188 video-codec@1c0e000 {
189 compatible = "allwinner,sun8i-h3-video-engine";
191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192 <&ccu CLK_DRAM_VE>;
193 clock-names = "ahb", "mod", "ram";
194 resets = <&ccu RST_BUS_VE>;
200 compatible = "allwinner,sun8i-h3-crypto";
203 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
204 clock-names = "bus", "mod";
205 resets = <&ccu RST_BUS_CE>;
209 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
218 interrupt-names = "gp",
225 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
226 clock-names = "bus", "core";
227 resets = <&ccu RST_BUS_GPU>;
228 operating-points-v2 = <&gpu_opp_table>;
231 ths: thermal-sensor@1c25000 {
232 compatible = "allwinner,sun8i-h3-ths";
235 resets = <&ccu RST_BUS_THS>;
236 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
237 clock-names = "bus", "mod";
238 nvmem-cells = <&ths_calibration>;
239 nvmem-cell-names = "calibration";
240 #thermal-sensor-cells = <0>;
244 thermal-zones {
245 cpu_thermal: cpu-thermal {
246 polling-delay-passive = <0>;
247 polling-delay = <0>;
248 thermal-sensors = <&ths>;
251 cpu_hot_trip: cpu-hot {
257 cpu_very_hot_trip: cpu-very-hot {
264 cooling-maps {
265 cpu-hot-limit {
267 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
277 &ccu {
278 compatible = "allwinner,sun8i-h3-ccu";
282 compatible = "allwinner,sun8i-h3-de2-clk";
286 compatible = "allwinner,sun8i-h3-mbus";
290 compatible = "allwinner,sun7i-a20-mmc";
291 clocks = <&ccu CLK_BUS_MMC0>,
292 <&ccu CLK_MMC0>,
293 <&ccu CLK_MMC0_OUTPUT>,
294 <&ccu CLK_MMC0_SAMPLE>;
295 clock-names = "ahb",
302 compatible = "allwinner,sun7i-a20-mmc";
303 clocks = <&ccu CLK_BUS_MMC1>,
304 <&ccu CLK_MMC1>,
305 <&ccu CLK_MMC1_OUTPUT>,
306 <&ccu CLK_MMC1_SAMPLE>;
307 clock-names = "ahb",
314 compatible = "allwinner,sun7i-a20-mmc";
315 clocks = <&ccu CLK_BUS_MMC2>,
316 <&ccu CLK_MMC2>,
317 <&ccu CLK_MMC2_OUTPUT>,
318 <&ccu CLK_MMC2_SAMPLE>;
319 clock-names = "ahb",
326 compatible = "allwinner,sun8i-h3-pinctrl";
330 compatible = "allwinner,sun8i-h3-rtc";
334 compatible = "allwinner,sun8i-h3-sid";