Lines Matching +full:ns +full:- +full:thermal
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
57 #address-cells = <1>;
58 #size-cells = <1>;
61 #address-cells = <1>;
62 #size-cells = <0>;
65 compatible = "arm,cortex-a7";
68 operating-points-v2 = <&cpu0_opp_table>;
69 cci-control-port = <&cci_control0>;
70 enable-method = "allwinner,sun8i-a83t-smp";
72 #cooling-cells = <2>;
76 compatible = "arm,cortex-a7";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cci-control-port = <&cci_control0>;
81 enable-method = "allwinner,sun8i-a83t-smp";
83 #cooling-cells = <2>;
87 compatible = "arm,cortex-a7";
90 operating-points-v2 = <&cpu0_opp_table>;
91 cci-control-port = <&cci_control0>;
92 enable-method = "allwinner,sun8i-a83t-smp";
94 #cooling-cells = <2>;
98 compatible = "arm,cortex-a7";
101 operating-points-v2 = <&cpu0_opp_table>;
102 cci-control-port = <&cci_control0>;
103 enable-method = "allwinner,sun8i-a83t-smp";
105 #cooling-cells = <2>;
109 compatible = "arm,cortex-a7";
112 operating-points-v2 = <&cpu1_opp_table>;
113 cci-control-port = <&cci_control1>;
114 enable-method = "allwinner,sun8i-a83t-smp";
116 #cooling-cells = <2>;
120 compatible = "arm,cortex-a7";
123 operating-points-v2 = <&cpu1_opp_table>;
124 cci-control-port = <&cci_control1>;
125 enable-method = "allwinner,sun8i-a83t-smp";
127 #cooling-cells = <2>;
131 compatible = "arm,cortex-a7";
134 operating-points-v2 = <&cpu1_opp_table>;
135 cci-control-port = <&cci_control1>;
136 enable-method = "allwinner,sun8i-a83t-smp";
138 #cooling-cells = <2>;
142 compatible = "arm,cortex-a7";
145 operating-points-v2 = <&cpu1_opp_table>;
146 cci-control-port = <&cci_control1>;
147 enable-method = "allwinner,sun8i-a83t-smp";
149 #cooling-cells = <2>;
154 compatible = "arm,armv7-timer";
162 #address-cells = <1>;
163 #size-cells = <1>;
167 osc24M: osc24M-clk {
168 #clock-cells = <0>;
169 compatible = "fixed-clock";
170 clock-frequency = <24000000>;
171 clock-accuracy = <50000>;
172 clock-output-names = "osc24M";
177 * It is an internal RC-based oscillator.
180 osc16M: osc16M-clk {
181 #clock-cells = <0>;
182 compatible = "fixed-clock";
183 clock-frequency = <16000000>;
184 clock-output-names = "osc16M";
187 osc16Md512: osc16Md512-clk {
188 #clock-cells = <0>;
189 compatible = "fixed-factor-clock";
190 clock-div = <512>;
191 clock-mult = <1>;
193 clock-output-names = "osc16M-d512";
197 de: display-engine {
198 compatible = "allwinner,sun8i-a83t-display-engine";
203 cpu0_opp_table: opp-table-cluster0 {
204 compatible = "operating-points-v2";
205 opp-shared;
207 opp-480000000 {
208 opp-hz = /bits/ 64 <480000000>;
209 opp-microvolt = <840000>;
210 clock-latency-ns = <244144>; /* 8 32k periods */
213 opp-600000000 {
214 opp-hz = /bits/ 64 <600000000>;
215 opp-microvolt = <840000>;
216 clock-latency-ns = <244144>; /* 8 32k periods */
219 opp-720000000 {
220 opp-hz = /bits/ 64 <720000000>;
221 opp-microvolt = <840000>;
222 clock-latency-ns = <244144>; /* 8 32k periods */
225 opp-864000000 {
226 opp-hz = /bits/ 64 <864000000>;
227 opp-microvolt = <840000>;
228 clock-latency-ns = <244144>; /* 8 32k periods */
231 opp-912000000 {
232 opp-hz = /bits/ 64 <912000000>;
233 opp-microvolt = <840000>;
234 clock-latency-ns = <244144>; /* 8 32k periods */
237 opp-1008000000 {
238 opp-hz = /bits/ 64 <1008000000>;
239 opp-microvolt = <840000>;
240 clock-latency-ns = <244144>; /* 8 32k periods */
243 opp-1128000000 {
244 opp-hz = /bits/ 64 <1128000000>;
245 opp-microvolt = <840000>;
246 clock-latency-ns = <244144>; /* 8 32k periods */
249 opp-1200000000 {
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <840000>;
252 clock-latency-ns = <244144>; /* 8 32k periods */
256 cpu1_opp_table: opp-table-cluster1 {
257 compatible = "operating-points-v2";
258 opp-shared;
260 opp-480000000 {
261 opp-hz = /bits/ 64 <480000000>;
262 opp-microvolt = <840000>;
263 clock-latency-ns = <244144>; /* 8 32k periods */
266 opp-600000000 {
267 opp-hz = /bits/ 64 <600000000>;
268 opp-microvolt = <840000>;
269 clock-latency-ns = <244144>; /* 8 32k periods */
272 opp-720000000 {
273 opp-hz = /bits/ 64 <720000000>;
274 opp-microvolt = <840000>;
275 clock-latency-ns = <244144>; /* 8 32k periods */
278 opp-864000000 {
279 opp-hz = /bits/ 64 <864000000>;
280 opp-microvolt = <840000>;
281 clock-latency-ns = <244144>; /* 8 32k periods */
284 opp-912000000 {
285 opp-hz = /bits/ 64 <912000000>;
286 opp-microvolt = <840000>;
287 clock-latency-ns = <244144>; /* 8 32k periods */
290 opp-1008000000 {
291 opp-hz = /bits/ 64 <1008000000>;
292 opp-microvolt = <840000>;
293 clock-latency-ns = <244144>; /* 8 32k periods */
296 opp-1128000000 {
297 opp-hz = /bits/ 64 <1128000000>;
298 opp-microvolt = <840000>;
299 clock-latency-ns = <244144>; /* 8 32k periods */
302 opp-1200000000 {
303 opp-hz = /bits/ 64 <1200000000>;
304 opp-microvolt = <840000>;
305 clock-latency-ns = <244144>; /* 8 32k periods */
310 compatible = "simple-bus";
311 #address-cells = <1>;
312 #size-cells = <1>;
316 compatible = "allwinner,sun8i-a83t-de2-clk";
320 clock-names = "bus",
323 #clock-cells = <1>;
324 #reset-cells = <1>;
328 compatible = "allwinner,sun8i-a83t-de2-rotate";
333 clock-names = "bus",
339 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
343 clock-names = "bus",
348 #address-cells = <1>;
349 #size-cells = <0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
358 remote-endpoint = <&tcon0_in_mixer0>;
363 remote-endpoint = <&tcon1_in_mixer0>;
370 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
374 clock-names = "bus",
379 #address-cells = <1>;
380 #size-cells = <0>;
383 #address-cells = <1>;
384 #size-cells = <0>;
389 remote-endpoint = <&tcon0_in_mixer1>;
394 remote-endpoint = <&tcon1_in_mixer1>;
401 compatible = "allwinner,sun8i-a83t-cpucfg";
406 compatible = "arm,cci-400";
407 #address-cells = <1>;
408 #size-cells = <1>;
412 cci_control0: slave-if@4000 {
413 compatible = "arm,cci-400-ctrl-if";
414 interface-type = "ace";
418 cci_control1: slave-if@5000 {
419 compatible = "arm,cci-400-ctrl-if";
420 interface-type = "ace";
425 compatible = "arm,cci-400-pmu,r1";
439 compatible = "allwinner,sun8i-a83t-system-controller",
444 dma: dma-controller@1c02000 {
445 compatible = "allwinner,sun8i-a83t-dma";
450 #dma-cells = <1>;
453 tcon0: lcd-controller@1c0c000 {
454 compatible = "allwinner,sun8i-a83t-tcon-lcd";
458 clock-names = "ahb", "tcon-ch0";
459 clock-output-names = "tcon-data-clock";
460 #clock-cells = <0>;
462 reset-names = "lcd", "lvds";
465 #address-cells = <1>;
466 #size-cells = <0>;
469 #address-cells = <1>;
470 #size-cells = <0>;
475 remote-endpoint = <&mixer0_out_tcon0>;
480 remote-endpoint = <&mixer1_out_tcon0>;
490 tcon1: lcd-controller@1c0d000 {
491 compatible = "allwinner,sun8i-a83t-tcon-tv";
495 clock-names = "ahb", "tcon-ch1";
497 reset-names = "lcd";
500 #address-cells = <1>;
501 #size-cells = <0>;
504 #address-cells = <1>;
505 #size-cells = <0>;
510 remote-endpoint = <&mixer0_out_tcon1>;
515 remote-endpoint = <&mixer1_out_tcon1>;
520 #address-cells = <1>;
521 #size-cells = <0>;
526 remote-endpoint = <&hdmi_in_tcon1>;
533 compatible = "allwinner,sun8i-a83t-mmc",
534 "allwinner,sun7i-a20-mmc";
540 clock-names = "ahb",
545 reset-names = "ahb";
548 #address-cells = <1>;
549 #size-cells = <0>;
553 compatible = "allwinner,sun8i-a83t-mmc",
554 "allwinner,sun7i-a20-mmc";
560 clock-names = "ahb",
565 reset-names = "ahb";
567 pinctrl-names = "default";
568 pinctrl-0 = <&mmc1_pins>;
570 #address-cells = <1>;
571 #size-cells = <0>;
575 compatible = "allwinner,sun8i-a83t-emmc";
581 clock-names = "ahb",
586 reset-names = "ahb";
589 #address-cells = <1>;
590 #size-cells = <0>;
594 compatible = "allwinner,sun8i-a83t-sid";
596 #address-cells = <1>;
597 #size-cells = <1>;
599 ths_calibration: thermal-sensor-calibration@34 {
605 compatible = "allwinner,sun8i-a83t-crypto";
610 clock-names = "bus", "mod";
614 compatible = "allwinner,sun8i-a83t-msgbox",
615 "allwinner,sun6i-a31-msgbox";
620 #mbox-cells = <1>;
624 compatible = "allwinner,sun8i-a83t-musb",
625 "allwinner,sun8i-a33-musb";
630 interrupt-names = "mc";
632 phy-names = "usb";
639 compatible = "allwinner,sun8i-a83t-usb-phy";
643 reg-names = "phy_ctrl",
650 clock-names = "usb0_phy",
657 reset-names = "usb0_reset",
661 #phy-cells = <1>;
665 compatible = "allwinner,sun8i-a83t-ehci",
666 "generic-ehci";
672 phy-names = "usb";
677 compatible = "allwinner,sun8i-a83t-ohci",
678 "generic-ohci";
684 phy-names = "usb";
689 compatible = "allwinner,sun8i-a83t-ehci",
690 "generic-ehci";
696 phy-names = "usb";
701 compatible = "allwinner,sun8i-a83t-ccu";
704 clock-names = "hosc", "losc";
705 #clock-cells = <1>;
706 #reset-cells = <1>;
710 compatible = "allwinner,sun8i-a83t-pinctrl";
711 interrupt-parent = <&r_intc>;
717 clock-names = "apb", "hosc", "losc";
718 gpio-controller;
719 interrupt-controller;
720 #interrupt-cells = <3>;
721 #gpio-cells = <3>;
723 /omit-if-no-ref/
724 csi_8bit_parallel_pins: csi-8bit-parallel-pins {
731 /omit-if-no-ref/
732 csi_mclk_pin: csi-mclk-pin {
737 emac_rgmii_pins: emac-rgmii-pins {
746 drive-strength = <40>;
749 hdmi_pins: hdmi-pins {
754 i2c0_pins: i2c0-pins {
759 i2c1_pins: i2c1-pins {
764 /omit-if-no-ref/
765 i2c2_pe_pins: i2c2-pe-pins {
770 i2c2_ph_pins: i2c2-ph-pins {
775 i2s1_pins: i2s1-pins {
781 lcd_lvds_pins: lcd-lvds-pins {
787 mmc0_pins: mmc0-pins {
791 drive-strength = <30>;
792 bias-pull-up;
795 mmc1_pins: mmc1-pins {
799 drive-strength = <30>;
800 bias-pull-up;
803 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
808 drive-strength = <30>;
809 bias-pull-up;
812 pwm_pin: pwm-pin {
817 spdif_tx_pin: spdif-tx-pin {
822 uart0_pb_pins: uart0-pb-pins {
827 uart0_pf_pins: uart0-pf-pins {
832 uart1_pins: uart1-pins {
837 uart1_rts_cts_pins: uart1-rts-cts-pins {
842 /omit-if-no-ref/
843 uart2_pb_pins: uart2-pb-pins {
850 compatible = "allwinner,sun8i-a23-timer";
858 compatible = "allwinner,sun6i-a31-wdt";
865 #sound-dai-cells = <0>;
866 compatible = "allwinner,sun8i-a83t-spdif",
867 "allwinner,sun8i-h3-spdif";
872 clock-names = "apb", "spdif";
874 dma-names = "tx";
875 pinctrl-names = "default";
876 pinctrl-0 = <&spdif_tx_pin>;
881 #sound-dai-cells = <0>;
882 compatible = "allwinner,sun8i-a83t-i2s";
886 clock-names = "apb", "mod";
889 dma-names = "rx", "tx";
894 #sound-dai-cells = <0>;
895 compatible = "allwinner,sun8i-a83t-i2s";
899 clock-names = "apb", "mod";
902 dma-names = "rx", "tx";
903 pinctrl-names = "default";
904 pinctrl-0 = <&i2s1_pins>;
909 #sound-dai-cells = <0>;
910 compatible = "allwinner,sun8i-a83t-i2s";
914 clock-names = "apb", "mod";
917 dma-names = "tx";
922 compatible = "allwinner,sun8i-a83t-pwm",
923 "allwinner,sun8i-h3-pwm";
926 #pwm-cells = <3>;
931 compatible = "snps,dw-apb-uart";
934 reg-shift = <2>;
935 reg-io-width = <4>;
942 compatible = "snps,dw-apb-uart";
945 reg-shift = <2>;
946 reg-io-width = <4>;
953 compatible = "snps,dw-apb-uart";
956 reg-shift = <2>;
957 reg-io-width = <4>;
964 compatible = "snps,dw-apb-uart";
967 reg-shift = <2>;
968 reg-io-width = <4>;
975 compatible = "snps,dw-apb-uart";
978 reg-shift = <2>;
979 reg-io-width = <4>;
986 compatible = "allwinner,sun8i-a83t-i2c",
987 "allwinner,sun6i-a31-i2c";
992 pinctrl-names = "default";
993 pinctrl-0 = <&i2c0_pins>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1000 compatible = "allwinner,sun8i-a83t-i2c",
1001 "allwinner,sun6i-a31-i2c";
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c1_pins>;
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1014 compatible = "allwinner,sun8i-a83t-i2c",
1015 "allwinner,sun6i-a31-i2c";
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1026 compatible = "allwinner,sun8i-a83t-emac";
1030 interrupt-names = "macirq";
1032 clock-names = "stmmaceth";
1034 reset-names = "stmmaceth";
1038 compatible = "snps,dwmac-mdio";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1044 gic: interrupt-controller@1c81000 {
1045 compatible = "arm,gic-400";
1050 interrupt-controller;
1051 #interrupt-cells = <3>;
1056 compatible = "allwinner,sun8i-a83t-csi";
1062 clock-names = "bus", "mod", "ram";
1068 compatible = "allwinner,sun8i-a83t-dw-hdmi";
1070 reg-io-width = <1>;
1074 clock-names = "iahb", "isfr", "tmds";
1076 reset-names = "ctrl";
1078 phy-names = "phy";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&hdmi_pins>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1091 remote-endpoint = <&tcon1_out_hdmi>;
1101 hdmi_phy: hdmi-phy@1ef0000 {
1102 compatible = "allwinner,sun8i-a83t-hdmi-phy";
1105 clock-names = "bus", "mod";
1107 reset-names = "phy";
1108 #phy-cells = <0>;
1111 r_intc: interrupt-controller@1f00c00 {
1112 compatible = "allwinner,sun8i-a83t-r-intc",
1113 "allwinner,sun6i-a31-r-intc";
1114 interrupt-controller;
1115 #interrupt-cells = <3>;
1121 compatible = "allwinner,sun8i-a83t-r-ccu";
1125 clock-names = "hosc", "losc", "iosc", "pll-periph";
1126 #clock-cells = <1>;
1127 #reset-cells = <1>;
1131 compatible = "allwinner,sun8i-a83t-r-cpucfg";
1136 compatible = "allwinner,sun8i-a83t-ir",
1137 "allwinner,sun6i-a31-ir";
1139 clock-names = "apb", "ir";
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&r_cir_pin>;
1149 compatible = "allwinner,sun8i-a83t-r-lradc";
1151 interrupt-parent = <&r_intc>;
1157 compatible = "allwinner,sun8i-a83t-r-pinctrl";
1159 interrupt-parent = <&r_intc>;
1163 clock-names = "apb", "hosc", "losc";
1164 gpio-controller;
1165 #gpio-cells = <3>;
1166 interrupt-controller;
1167 #interrupt-cells = <3>;
1169 r_cir_pin: r-cir-pin {
1174 r_rsb_pins: r-rsb-pins {
1177 drive-strength = <20>;
1178 bias-pull-up;
1183 compatible = "allwinner,sun8i-a83t-rsb",
1184 "allwinner,sun8i-a23-rsb";
1188 clock-frequency = <3000000>;
1190 pinctrl-names = "default";
1191 pinctrl-0 = <&r_rsb_pins>;
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1197 ths: thermal-sensor@1f04000 {
1198 compatible = "allwinner,sun8i-a83t-ths";
1201 nvmem-cells = <&ths_calibration>;
1202 nvmem-cell-names = "calibration";
1203 #thermal-sensor-cells = <1>;
1207 thermal-zones {
1208 cpu0_thermal: cpu0-thermal {
1209 polling-delay-passive = <0>;
1210 polling-delay = <0>;
1211 thermal-sensors = <&ths 0>;
1214 cpu0_hot: cpu-hot {
1220 cpu0_very_hot: cpu-very-hot {
1227 cooling-maps {
1228 cpu-hot-limit {
1230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1238 cpu1_thermal: cpu1-thermal {
1239 polling-delay-passive = <0>;
1240 polling-delay = <0>;
1241 thermal-sensors = <&ths 1>;
1244 cpu1_hot: cpu-hot {
1250 cpu1_very_hot: cpu-very-hot {
1257 cooling-maps {
1258 cpu-hot-limit {
1260 cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1268 gpu_thermal: gpu-thermal {
1269 polling-delay-passive = <0>;
1270 polling-delay = <0>;
1271 thermal-sensors = <&ths 2>;