Lines Matching +full:0 +full:x01d00000
91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
158 reg = <0x01c02000 0x1000>;
167 reg = <0x01c03000 0x1000>;
176 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
179 #size-cells = <0>;
184 reg = <0x01c0c000 0x1000>;
194 #clock-cells = <0>;
203 #size-cells = <0>;
205 tcon0_in: port@0 {
206 reg = <0>;
221 reg = <0x01c0f000 0x1000>;
234 pinctrl-0 = <&mmc0_pins>;
237 #size-cells = <0>;
242 reg = <0x01c10000 0x1000>;
256 #size-cells = <0>;
261 reg = <0x01c11000 0x1000>;
275 #size-cells = <0>;
280 reg = <0x01c19000 0x0400>;
285 phys = <&usbphy 0>;
287 extcon = <&usbphy 0>;
311 reg = <0x01c1a000 0x100>;
322 reg = <0x01c1a400 0x100>;
332 reg = <0x01c20000 0x400>;
341 reg = <0x01c20800 0x400>;
455 reg = <0x01c20c00 0xa0>;
463 reg = <0x01c20ca0 0x20>;
470 reg = <0x01c21400 0xc>;
478 reg = <0x01c22800 0x100>;
486 reg = <0x01c28000 0x400>;
487 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
499 reg = <0x01c28400 0x400>;
512 reg = <0x01c28800 0x400>;
525 reg = <0x01c28c00 0x400>;
538 reg = <0x01c29000 0x400>;
551 reg = <0x01c2ac00 0x400>;
556 pinctrl-0 = <&i2c0_pins>;
559 #size-cells = <0>;
564 reg = <0x01c2b000 0x400>;
569 pinctrl-0 = <&i2c1_pins>;
572 #size-cells = <0>;
577 reg = <0x01c2b400 0x400>;
582 pinctrl-0 = <&i2c2_pins>;
585 #size-cells = <0>;
591 reg = <0x01c40000 0x10000>;
617 reg = <0x01c81000 0x1000>,
618 <0x01c82000 0x2000>,
619 <0x01c84000 0x2000>,
620 <0x01c86000 0x2000>;
628 reg = <0x01e00000 0x20000>;
638 #size-cells = <0>;
652 reg = <0x01e60000 0x10000>;
662 #size-cells = <0>;
664 be0_in: port@0 {
665 reg = <0>;
684 reg = <0x01e70000 0x10000>;
693 #size-cells = <0>;
695 drc0_in: port@0 {
696 reg = <0>;
715 reg = <0x01f00000 0x400>;
728 reg = <0x01f00c00 0x400>;
734 reg = <0x01f01400 0x200>;
738 #clock-cells = <0>;
747 #clock-cells = <0>;
756 #clock-cells = <0>;
782 reg = <0x01f01c00 0x300>;
787 reg = <0x01f02800 0x400>;
799 reg = <0x01f02400 0x400>;
802 pinctrl-0 = <&r_i2c_pins>;
807 #size-cells = <0>;
812 reg = <0x01f02c00 0x400>;
815 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
843 reg = <0x01f03400 0x400>;
849 pinctrl-0 = <&r_rsb_pins>;
852 #size-cells = <0>;