Lines Matching +full:0 +full:x01c0f000
101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
247 reg = <0x01c20164 0x4>;
269 reg = <0x01c00000 0x30>;
274 sram_a: sram@0 {
276 reg = <0x00000000 0xc000>;
279 ranges = <0 0x00000000 0xc000>;
284 reg = <0x8000 0x4000>;
291 reg = <0x00010000 0x1000>;
294 ranges = <0 0x00010000 0x1000>;
296 otg_sram: sram-section@0 {
299 reg = <0x0000 0x1000>;
306 reg = <0x01d00000 0xd0000>;
309 ranges = <0 0x01d00000 0xd0000>;
311 ve_sram: sram-section@0 {
314 reg = <0x000000 0x80000>;
323 reg = <0x01c00030 0x0c>;
324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
329 reg = <0x01c02000 0x1000>;
337 reg = <0x01c03000 0x1000>;
345 #size-cells = <0>;
350 reg = <0x01c05000 0x1000>;
359 #size-cells = <0>;
365 reg = <0x01c06000 0x1000>;
374 #size-cells = <0>;
380 reg = <0x01c09000 0x1000>;
390 reg = <0x01c0b000 0x1000>;
399 reg = <0x01c0b080 0x14>;
402 #size-cells = <0>;
408 reg = <0x01c0c000 0x1000>;
419 #clock-cells = <0>;
424 #size-cells = <0>;
426 tcon0_in: port@0 {
428 #size-cells = <0>;
429 reg = <0>;
431 tcon0_in_be0: endpoint@0 {
432 reg = <0>;
444 #size-cells = <0>;
459 reg = <0x01c0d000 0x1000>;
470 #clock-cells = <0>;
475 #size-cells = <0>;
477 tcon1_in: port@0 {
479 #size-cells = <0>;
480 reg = <0>;
482 tcon1_in_be0: endpoint@0 {
483 reg = <0>;
495 #size-cells = <0>;
509 reg = <0x01c0e000 0x1000>;
520 reg = <0x01c0f000 0x1000>;
531 pinctrl-0 = <&mmc0_pins>;
534 #size-cells = <0>;
539 reg = <0x01c10000 0x1000>;
551 #size-cells = <0>;
556 reg = <0x01c11000 0x1000>;
567 pinctrl-0 = <&mmc2_pins>;
570 #size-cells = <0>;
575 reg = <0x01c12000 0x1000>;
586 pinctrl-0 = <&mmc3_pins>;
589 #size-cells = <0>;
594 reg = <0x01c13000 0x0400>;
598 phys = <&usbphy 0>;
600 extcon = <&usbphy 0>;
609 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
622 reg = <0x01c14000 0x100>;
632 reg = <0x01c14400 0x100>;
643 reg = <0x01c15000 0x1000>;
652 reg = <0x01c16000 0x1000>;
657 clock-names = "ahb", "mod", "pll-0", "pll-1";
666 #size-cells = <0>;
668 hdmi_in: port@0 {
670 #size-cells = <0>;
671 reg = <0>;
673 hdmi_in_tcon0: endpoint@0 {
674 reg = <0>;
692 reg = <0x01c17000 0x1000>;
701 #size-cells = <0>;
707 reg = <0x01c18000 0x1000>;
715 reg = <0x01c1c000 0x100>;
725 reg = <0x01c1c400 0x100>;
736 reg = <0x01c1d000 0x1000>;
746 reg = <0x01c1f000 0x1000>;
755 #size-cells = <0>;
761 reg = <0x01c20000 0x400>;
770 reg = <0x01c20800 0x400>;
977 ps2_0_pins: ps2-0-pins {
1184 reg = <0x01c20c00 0x90>;
1196 reg = <0x01c20c90 0x10>;
1203 reg = <0x01c20d00 0x20>;
1209 reg = <0x01c20e00 0xc>;
1216 #sound-dai-cells = <0>;
1218 reg = <0x01c21000 0x400>;
1233 reg = <0x01c21800 0x40>;
1242 reg = <0x01c21c00 0x40>;
1247 #sound-dai-cells = <0>;
1249 reg = <0x01c22000 0x400>;
1260 #sound-dai-cells = <0>;
1262 reg = <0x01c22400 0x400>;
1274 reg = <0x01c22800 0x100>;
1280 #sound-dai-cells = <0>;
1282 reg = <0x01c22c00 0x40>;
1294 reg = <0x01c23800 0x200>;
1298 #sound-dai-cells = <0>;
1300 reg = <0x01c24400 0x400>;
1312 reg = <0x01c25000 0x100>;
1314 #thermal-sensor-cells = <0>;
1319 reg = <0x01c28000 0x400>;
1329 reg = <0x01c28400 0x400>;
1339 reg = <0x01c28800 0x400>;
1349 reg = <0x01c28c00 0x400>;
1359 reg = <0x01c29000 0x400>;
1369 reg = <0x01c29400 0x400>;
1379 reg = <0x01c29800 0x400>;
1389 reg = <0x01c29c00 0x400>;
1399 reg = <0x01c2a000 0x400>;
1407 reg = <0x01c2a400 0x400>;
1416 reg = <0x01c2ac00 0x400>;
1420 pinctrl-0 = <&i2c0_pins>;
1423 #size-cells = <0>;
1429 reg = <0x01c2b000 0x400>;
1433 pinctrl-0 = <&i2c1_pins>;
1436 #size-cells = <0>;
1442 reg = <0x01c2b400 0x400>;
1446 pinctrl-0 = <&i2c2_pins>;
1449 #size-cells = <0>;
1455 reg = <0x01c2b800 0x400>;
1459 pinctrl-0 = <&i2c3_pins>;
1462 #size-cells = <0>;
1468 reg = <0x01c2bc00 0x400>;
1477 reg = <0x01c2c000 0x400>;
1482 #size-cells = <0>;
1487 reg = <0x01c40000 0x10000>;
1512 reg = <0x01c50000 0x10000>;
1525 #size-cells = <0>;
1531 reg = <0x01c60000 0x1000>;
1541 reg = <0x01c81000 0x1000>,
1542 <0x01c82000 0x2000>,
1543 <0x01c84000 0x2000>,
1544 <0x01c86000 0x2000>;
1552 reg = <0x01e00000 0x20000>;
1562 #size-cells = <0>;
1566 #size-cells = <0>;
1569 fe0_out_be0: endpoint@0 {
1570 reg = <0>;
1584 reg = <0x01e20000 0x20000>;
1594 #size-cells = <0>;
1598 #size-cells = <0>;
1601 fe1_out_be0: endpoint@0 {
1602 reg = <0>;
1616 reg = <0x01e40000 0x10000>;
1626 #size-cells = <0>;
1628 be1_in: port@0 {
1630 #size-cells = <0>;
1631 reg = <0>;
1633 be1_in_fe0: endpoint@0 {
1634 reg = <0>;
1646 #size-cells = <0>;
1649 be1_out_tcon0: endpoint@0 {
1650 reg = <0>;
1664 reg = <0x01e60000 0x10000>;
1674 #size-cells = <0>;
1676 be0_in: port@0 {
1678 #size-cells = <0>;
1679 reg = <0>;
1681 be0_in_fe0: endpoint@0 {
1682 reg = <0>;
1694 #size-cells = <0>;
1697 be0_out_tcon0: endpoint@0 {
1698 reg = <0>;