Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ccu
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
98 "simple-framebuffer";
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
110 #address-cells = <1>;
111 #size-cells = <0>;
114 compatible = "arm,cortex-a8";
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
118 operating-points =
124 #cooling-cells = <2>;
128 thermal-zones {
129 cpu-thermal {
131 polling-delay-passive = <250>;
132 polling-delay = <1000>;
133 thermal-sensors = <&rtp>;
135 cooling-maps {
138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
143 cpu_alert0: cpu-alert0 {
150 cpu_crit: cpu-crit {
161 #address-cells = <1>;
162 #size-cells = <1>;
165 osc24M: clk-24M {
166 #clock-cells = <0>;
167 compatible = "fixed-clock";
168 clock-frequency = <24000000>;
169 clock-output-names = "osc24M";
172 osc32k: clk-32k {
173 #clock-cells = <0>;
174 compatible = "fixed-clock";
175 clock-frequency = <32768>;
176 clock-output-names = "osc32k";
180 de: display-engine {
181 compatible = "allwinner,sun4i-a10-display-engine";
187 compatible = "arm,cortex-a8-pmu";
191 reserved-memory {
192 #address-cells = <1>;
193 #size-cells = <1>;
197 default-pool {
198 compatible = "shared-dma-pool";
200 alloc-ranges = <0x40000000 0x10000000>;
202 linux,cma-default;
207 compatible = "simple-bus";
208 #address-cells = <1>;
209 #size-cells = <1>;
212 system-control@1c00000 {
213 compatible = "allwinner,sun4i-a10-system-control";
215 #address-cells = <1>;
216 #size-cells = <1>;
220 compatible = "mmio-sram";
222 #address-cells = <1>;
223 #size-cells = <1>;
226 emac_sram: sram-section@8000 {
227 compatible = "allwinner,sun4i-a10-sram-a3-a4";
234 compatible = "mmio-sram";
236 #address-cells = <1>;
237 #size-cells = <1>;
240 otg_sram: sram-section@0 {
241 compatible = "allwinner,sun4i-a10-sram-d";
248 compatible = "mmio-sram";
250 #address-cells = <1>;
251 #size-cells = <1>;
254 ve_sram: sram-section@0 {
255 compatible = "allwinner,sun4i-a10-sram-c1";
261 dma: dma-controller@1c02000 {
262 compatible = "allwinner,sun4i-a10-dma";
265 clocks = <&ccu CLK_AHB_DMA>;
266 #dma-cells = <2>;
269 nfc: nand-controller@1c03000 {
270 compatible = "allwinner,sun4i-a10-nand";
273 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
274 clock-names = "ahb", "mod";
276 dma-names = "rxtx";
278 #address-cells = <1>;
279 #size-cells = <0>;
283 compatible = "allwinner,sun4i-a10-spi";
286 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
287 clock-names = "ahb", "mod";
290 dma-names = "rx", "tx";
292 #address-cells = <1>;
293 #size-cells = <0>;
297 compatible = "allwinner,sun4i-a10-spi";
300 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
301 clock-names = "ahb", "mod";
304 dma-names = "rx", "tx";
305 pinctrl-names = "default";
306 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
308 #address-cells = <1>;
309 #size-cells = <0>;
313 compatible = "allwinner,sun4i-a10-emac";
316 clocks = <&ccu CLK_AHB_EMAC>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&emac_pins>;
324 compatible = "allwinner,sun4i-a10-mdio";
327 #address-cells = <1>;
328 #size-cells = <0>;
331 tcon0: lcd-controller@1c0c000 {
332 compatible = "allwinner,sun4i-a10-tcon";
335 resets = <&ccu RST_TCON0>;
336 reset-names = "lcd";
337 clocks = <&ccu CLK_AHB_LCD0>,
338 <&ccu CLK_TCON0_CH0>,
339 <&ccu CLK_TCON0_CH1>;
340 clock-names = "ahb",
341 "tcon-ch0",
342 "tcon-ch1";
343 clock-output-names = "tcon0-pixel-clock";
344 #clock-cells = <0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
358 remote-endpoint = <&be0_out_tcon0>;
363 remote-endpoint = <&be1_out_tcon0>;
368 #address-cells = <1>;
369 #size-cells = <0>;
374 remote-endpoint = <&hdmi_in_tcon0>;
375 allwinner,tcon-channel = <1>;
381 tcon1: lcd-controller@1c0d000 {
382 compatible = "allwinner,sun4i-a10-tcon";
385 resets = <&ccu RST_TCON1>;
386 reset-names = "lcd";
387 clocks = <&ccu CLK_AHB_LCD1>,
388 <&ccu CLK_TCON1_CH0>,
389 <&ccu CLK_TCON1_CH1>;
390 clock-names = "ahb",
391 "tcon-ch0",
392 "tcon-ch1";
393 clock-output-names = "tcon1-pixel-clock";
394 #clock-cells = <0>;
398 #address-cells = <1>;
399 #size-cells = <0>;
402 #address-cells = <1>;
403 #size-cells = <0>;
408 remote-endpoint = <&be0_out_tcon1>;
413 remote-endpoint = <&be1_out_tcon1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
424 remote-endpoint = <&hdmi_in_tcon1>;
425 allwinner,tcon-channel = <1>;
431 video-codec@1c0e000 {
432 compatible = "allwinner,sun4i-a10-video-engine";
434 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
435 <&ccu CLK_DRAM_VE>;
436 clock-names = "ahb", "mod", "ram";
437 resets = <&ccu RST_VE>;
443 compatible = "allwinner,sun4i-a10-mmc";
445 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
446 clock-names = "ahb", "mmc";
448 pinctrl-names = "default";
449 pinctrl-0 = <&mmc0_pins>;
451 #address-cells = <1>;
452 #size-cells = <0>;
456 compatible = "allwinner,sun4i-a10-mmc";
458 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
459 clock-names = "ahb", "mmc";
462 #address-cells = <1>;
463 #size-cells = <0>;
467 compatible = "allwinner,sun4i-a10-mmc";
469 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
470 clock-names = "ahb", "mmc";
473 #address-cells = <1>;
474 #size-cells = <0>;
478 compatible = "allwinner,sun4i-a10-mmc";
480 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
481 clock-names = "ahb", "mmc";
484 #address-cells = <1>;
485 #size-cells = <0>;
489 compatible = "allwinner,sun4i-a10-musb";
491 clocks = <&ccu CLK_AHB_OTG>;
493 interrupt-names = "mc";
495 phy-names = "usb";
503 #phy-cells = <1>;
504 compatible = "allwinner,sun4i-a10-usb-phy";
506 reg-names = "phy_ctrl", "pmu1", "pmu2";
507 clocks = <&ccu CLK_USB_PHY>;
508 clock-names = "usb_phy";
509 resets = <&ccu RST_USB_PHY0>,
510 <&ccu RST_USB_PHY1>,
511 <&ccu RST_USB_PHY2>;
512 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
517 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
520 clocks = <&ccu CLK_AHB_EHCI0>;
522 phy-names = "usb";
527 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
530 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
532 phy-names = "usb";
536 crypto: crypto-engine@1c15000 {
537 compatible = "allwinner,sun4i-a10-crypto";
540 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
541 clock-names = "ahb", "mod";
545 compatible = "allwinner,sun4i-a10-hdmi";
548 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
549 <&ccu CLK_PLL_VIDEO0_2X>,
550 <&ccu CLK_PLL_VIDEO1_2X>;
551 clock-names = "ahb", "mod", "pll-0", "pll-1";
555 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
559 #address-cells = <1>;
560 #size-cells = <0>;
563 #address-cells = <1>;
564 #size-cells = <0>;
569 remote-endpoint = <&tcon0_out_hdmi>;
574 remote-endpoint = <&tcon1_out_hdmi>;
585 compatible = "allwinner,sun4i-a10-spi";
588 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
589 clock-names = "ahb", "mod";
592 dma-names = "rx", "tx";
594 #address-cells = <1>;
595 #size-cells = <0>;
599 compatible = "allwinner,sun4i-a10-ahci";
602 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
607 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
610 clocks = <&ccu CLK_AHB_EHCI1>;
612 phy-names = "usb";
617 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
620 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
622 phy-names = "usb";
627 compatible = "allwinner,sun4i-a10-csi1";
630 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
631 clock-names = "bus", "ram";
632 resets = <&ccu RST_CSI1>;
637 compatible = "allwinner,sun4i-a10-spi";
640 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
641 clock-names = "ahb", "mod";
644 dma-names = "rx", "tx";
646 #address-cells = <1>;
647 #size-cells = <0>;
650 ccu: clock@1c20000 { label
651 compatible = "allwinner,sun4i-a10-ccu";
654 clock-names = "hosc", "losc";
655 #clock-cells = <1>;
656 #reset-cells = <1>;
659 intc: interrupt-controller@1c20400 {
660 compatible = "allwinner,sun4i-a10-ic";
662 interrupt-controller;
663 #interrupt-cells = <1>;
667 compatible = "allwinner,sun4i-a10-pinctrl";
670 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
671 clock-names = "apb", "hosc", "losc";
672 gpio-controller;
673 interrupt-controller;
674 #interrupt-cells = <3>;
675 #gpio-cells = <3>;
677 can0_ph_pins: can0-ph-pins {
682 /omit-if-no-ref/
683 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
690 /omit-if-no-ref/
691 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
701 /omit-if-no-ref/
702 csi1_clk_pg_pin: csi1-clk-pg-pin {
707 emac_pins: emac0-pins {
716 i2c0_pins: i2c0-pins {
721 i2c1_pins: i2c1-pins {
726 i2c2_pins: i2c2-pins {
731 ir0_rx_pins: ir0-rx-pin {
736 ir0_tx_pins: ir0-tx-pin {
741 ir1_rx_pins: ir1-rx-pin {
746 ir1_tx_pins: ir1-tx-pin {
751 mmc0_pins: mmc0-pins {
755 drive-strength = <30>;
756 bias-pull-up;
759 ps2_ch0_pins: ps2-ch0-pins {
764 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
769 pwm0_pin: pwm0-pin {
774 pwm1_pin: pwm1-pin {
779 spdif_tx_pin: spdif-tx-pin {
782 bias-pull-up;
785 spi0_pi_pins: spi0-pi-pins {
790 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
795 spi1_pins: spi1-pins {
800 spi1_cs0_pin: spi1-cs0-pin {
805 spi2_pb_pins: spi2-pb-pins {
810 spi2_pc_pins: spi2-pc-pins {
815 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
820 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
825 uart0_pb_pins: uart0-pb-pins {
830 uart0_pf_pins: uart0-pf-pins {
835 uart1_pins: uart1-pins {
842 compatible = "allwinner,sun4i-a10-timer";
854 compatible = "allwinner,sun4i-a10-wdt";
861 compatible = "allwinner,sun4i-a10-rtc";
867 compatible = "allwinner,sun4i-a10-pwm";
870 #pwm-cells = <3>;
875 #sound-dai-cells = <0>;
876 compatible = "allwinner,sun4i-a10-spdif";
879 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
880 clock-names = "apb", "spdif";
883 dma-names = "rx", "tx";
888 compatible = "allwinner,sun4i-a10-ir";
889 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
890 clock-names = "apb", "ir";
897 compatible = "allwinner,sun4i-a10-ir";
898 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
899 clock-names = "apb", "ir";
906 #sound-dai-cells = <0>;
907 compatible = "allwinner,sun4i-a10-i2s";
910 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
911 clock-names = "apb", "mod";
914 dma-names = "rx", "tx";
919 compatible = "allwinner,sun4i-a10-lradc-keys";
926 #sound-dai-cells = <0>;
927 compatible = "allwinner,sun4i-a10-codec";
930 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
931 clock-names = "apb", "codec";
934 dma-names = "rx", "tx";
939 compatible = "allwinner,sun4i-a10-sid";
944 compatible = "allwinner,sun4i-a10-ts";
947 #thermal-sensor-cells = <0>;
951 compatible = "snps,dw-apb-uart";
954 reg-shift = <2>;
955 reg-io-width = <4>;
956 clocks = <&ccu CLK_APB1_UART0>;
961 compatible = "snps,dw-apb-uart";
964 reg-shift = <2>;
965 reg-io-width = <4>;
966 clocks = <&ccu CLK_APB1_UART1>;
971 compatible = "snps,dw-apb-uart";
974 reg-shift = <2>;
975 reg-io-width = <4>;
976 clocks = <&ccu CLK_APB1_UART2>;
981 compatible = "snps,dw-apb-uart";
984 reg-shift = <2>;
985 reg-io-width = <4>;
986 clocks = <&ccu CLK_APB1_UART3>;
991 compatible = "snps,dw-apb-uart";
994 reg-shift = <2>;
995 reg-io-width = <4>;
996 clocks = <&ccu CLK_APB1_UART4>;
1001 compatible = "snps,dw-apb-uart";
1004 reg-shift = <2>;
1005 reg-io-width = <4>;
1006 clocks = <&ccu CLK_APB1_UART5>;
1011 compatible = "snps,dw-apb-uart";
1014 reg-shift = <2>;
1015 reg-io-width = <4>;
1016 clocks = <&ccu CLK_APB1_UART6>;
1021 compatible = "snps,dw-apb-uart";
1024 reg-shift = <2>;
1025 reg-io-width = <4>;
1026 clocks = <&ccu CLK_APB1_UART7>;
1031 compatible = "allwinner,sun4i-a10-ps2";
1034 clocks = <&ccu CLK_APB1_PS20>;
1039 compatible = "allwinner,sun4i-a10-ps2";
1042 clocks = <&ccu CLK_APB1_PS21>;
1047 compatible = "allwinner,sun4i-a10-i2c";
1050 clocks = <&ccu CLK_APB1_I2C0>;
1051 pinctrl-names = "default";
1052 pinctrl-0 = <&i2c0_pins>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1059 compatible = "allwinner,sun4i-a10-i2c";
1062 clocks = <&ccu CLK_APB1_I2C1>;
1063 pinctrl-names = "default";
1064 pinctrl-0 = <&i2c1_pins>;
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1071 compatible = "allwinner,sun4i-a10-i2c";
1074 clocks = <&ccu CLK_APB1_I2C2>;
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&i2c2_pins>;
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1083 compatible = "allwinner,sun4i-a10-can";
1086 clocks = <&ccu CLK_APB1_CAN>;
1091 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1098 interrupt-names = "gp",
1103 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1104 clock-names = "bus", "core";
1105 resets = <&ccu RST_GPU>;
1107 assigned-clocks = <&ccu CLK_GPU>;
1108 assigned-clock-rates = <384000000>;
1111 fe0: display-frontend@1e00000 {
1112 compatible = "allwinner,sun4i-a10-display-frontend";
1115 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1116 <&ccu CLK_DRAM_DE_FE0>;
1117 clock-names = "ahb", "mod",
1119 resets = <&ccu RST_DE_FE0>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1132 remote-endpoint = <&be0_in_fe0>;
1137 remote-endpoint = <&be1_in_fe0>;
1143 fe1: display-frontend@1e20000 {
1144 compatible = "allwinner,sun4i-a10-display-frontend";
1147 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1148 <&ccu CLK_DRAM_DE_FE1>;
1149 clock-names = "ahb", "mod",
1151 resets = <&ccu RST_DE_FE1>;
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1164 remote-endpoint = <&be0_in_fe1>;
1169 remote-endpoint = <&be1_in_fe1>;
1175 be1: display-backend@1e40000 {
1176 compatible = "allwinner,sun4i-a10-display-backend";
1179 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1180 <&ccu CLK_DRAM_DE_BE1>;
1181 clock-names = "ahb", "mod",
1183 resets = <&ccu RST_DE_BE1>;
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 remote-endpoint = <&fe0_out_be1>;
1201 remote-endpoint = <&fe1_out_be1>;
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1212 remote-endpoint = <&tcon0_in_be1>;
1217 remote-endpoint = <&tcon1_in_be1>;
1223 be0: display-backend@1e60000 {
1224 compatible = "allwinner,sun4i-a10-display-backend";
1227 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1228 <&ccu CLK_DRAM_DE_BE0>;
1229 clock-names = "ahb", "mod",
1231 resets = <&ccu RST_DE_BE0>;
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1244 remote-endpoint = <&fe0_out_be0>;
1249 remote-endpoint = <&fe1_out_be0>;
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1260 remote-endpoint = <&tcon0_in_be0>;
1265 remote-endpoint = <&tcon1_in_be0>;