Lines Matching +full:0 +full:x0007b000
15 #define OF_DT_MAGIC 0xd00dfeed
17 #define OF_DT_MAGIC 0xedfe0dd0
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
69 mov \rb, #0x80000000 @ physical base address
70 add \rb, \rb, #0x00010000 @ Ser1
98 kputc #'0'
102 kputc #'0'
107 kputc #'0'
111 kputc #'0'
127 kputc #'0'
132 kputc #'0'
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
146 ARM( .inst 0xf57ff06f @ v7+ isb )
218 .word 0x04030201 @ endianness flag
219 .word 0x45454545 @ another magic number to indicate
241 mov r0, #0x17 @ angel_SWIreason_EnterSVC
242 ARM( swi 0x123456 ) @ angel_SWI_ARM
243 THUMB( svc 0xab ) @ angel_SWI_THUMB
280 and r0, r0, #0xf8000000
351 mov r5, #0 @ init dtb size to 0
367 ldr lr, [r6, #0]
406 * pointed by r8. Try the typical 0x100 offset from start
412 add r0, r0, #0x100
552 * r5 = appended dtb size (0 if not present)
578 1: ldr r1, [r11, #0] @ relocate entries in the GOT
597 1: ldr r1, [r11, #0] @ relocate entries in the GOT
606 not_relocated: mov r0, #0
651 __HVC(0) @ otherwise bounce to hyp mode
680 params: ldr r0, =0x10000100 @ params_phys for RPC
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
699 and \tmp, \tmp, #0xf @ cache line size encoding
730 mov r0, #0x3f @ 4G, the whole
731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
732 mcr p15, 0, r0, c6, c7, 1
734 mov r0, #0x80 @ PR7
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
739 mov r0, #0xc000
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
743 mov r0, #0
744 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
747 mrc p15, 0, r0, c1, c0, 0 @ read control reg
749 orr r0, r0, #0x002d @ .... .... ..1. 11.1
750 orr r0, r0, #0x1000 @ ...1 .... .... ....
752 mcr p15, 0, r0, c1, c0, 0 @ write control reg
754 mov r0, #0
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
760 mov r0, #0x3f @ 4G, the whole
761 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
763 mov r0, #0x80 @ PR7
764 mcr p15, 0, r0, c2, c0, 0 @ cache on
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
767 mov r0, #0xc000
768 mcr p15, 0, r0, c5, c0, 0 @ access permission
770 mov r0, #0
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
776 mrc p15, 0, r0, c1, c0, 0 @ read control reg
778 orr r0, r0, #0x000d @ .... .... .... 11.1
780 mov r0, #0
781 mcr p15, 0, r0, c1, c0, 0 @ write control reg
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
788 #define CB_BITS 0x08
790 #define CB_BITS 0x0c
794 bic r3, r3, #0xff @ Align the pointer
795 bic r3, r3, #0x3f00
803 add r10, r9, #0x10000000 @ a reasonable RAM size
804 mov r1, #0x12 @ XN|U + section mapping
809 bic r1, r1, #0x1c @ clear XN|U + C + B
810 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
822 orr r1, r6, #0x04 @ ensure B is set for this
837 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
840 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
846 mcr p15, 7, r0, c15, c0, 0
852 mov r6, #CB_BITS | 0x12 @ U
854 mov r0, #0
855 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
856 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
857 mrc p15, 0, r0, c1, c0, 0 @ read control reg
858 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
859 orr r0, r0, #0x0030
862 mov r0, #0
863 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
871 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
872 tst r11, #0xf @ VMSA
873 movne r6, #CB_BITS | 0x02 @ !XN
875 mov r0, #0
876 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
877 tst r11, #0xf @ VMSA
878 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
880 mrc p15, 0, r0, c1, c0, 0 @ read control reg
882 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
883 orr r0, r0, #0x003c @ write buffer
889 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
891 movne r1, #0xfffffffd @ domain 0 = client
893 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
894 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
895 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
896 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
898 mcr p15, 0, r0, c7, c5, 4 @ ISB
899 mcr p15, 0, r0, c1, c0, 0 @ load control register
900 mrc p15, 0, r0, c1, c0, 0 @ and read it back
901 mov r0, #0
902 mcr p15, 0, r0, c7, c5, 4 @ ISB
907 mov r6, #CB_BITS | 0x12 @ U
909 mov r0, #0
910 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
911 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
912 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
913 mrc p15, 0, r0, c1, c0, 0 @ read control reg
914 orr r0, r0, #0x1000 @ I-cache enable
916 mov r0, #0
917 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
923 orr r0, r0, #0x000d @ Write buffer, mmu
926 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
927 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
930 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
931 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
953 mrc p15, 0, r9, c0, c0 @ get processor ID
967 1: ldr r1, [r12, #0] @ get value
985 * We match an entry using: ((real_id ^ match) & mask) == 0
994 .word 0x41000000 @ old ARM ID
995 .word 0xff00f000
1003 .word 0x41007000 @ ARM7/710
1004 .word 0xfff8fe00
1012 .word 0x41807200 @ ARM720T (writethrough)
1013 .word 0xffffff00
1019 .word 0x41007400 @ ARM74x
1020 .word 0xff00ff00
1025 .word 0x41009400 @ ARM94x
1026 .word 0xff00ff00
1031 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1032 .word 0xff0ffff0
1037 .word 0x00007000 @ ARM7 IDs
1038 .word 0x0000f000
1048 .word 0x4401a100 @ sa110 / sa1100
1049 .word 0xffffffe0
1054 .word 0x6901b110 @ sa1110
1055 .word 0xfffffff0
1060 .word 0x56056900
1061 .word 0xffffff00 @ PXA9xx
1066 .word 0x56158000 @ PXA168
1067 .word 0xfffff000
1072 .word 0x56050000 @ Feroceon
1073 .word 0xff0f0000
1080 .long 0x41009260 @ Old Feroceon
1081 .long 0xff00fff0
1087 .word 0x66015261 @ FA526
1088 .word 0xff01fff1
1095 .word 0x00020000 @ ARMv4T
1096 .word 0x000f0000
1101 .word 0x00050000 @ ARMv5TE
1102 .word 0x000f0000
1107 .word 0x00060000 @ ARMv5TEJ
1108 .word 0x000f0000
1113 .word 0x0007b000 @ ARMv6
1114 .word 0x000ff000
1119 .word 0x000f0000 @ new CPU Id
1120 .word 0x000f0000
1125 .word 0 @ unrecognised type
1126 .word 0
1142 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1160 mrc p15, 0, r0, c1, c0
1161 bic r0, r0, #0x000d
1162 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1163 mov r0, #0
1164 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1165 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1166 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1170 mrc p15, 0, r0, c1, c0
1171 bic r0, r0, #0x000d
1172 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1173 mov r0, #0
1174 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1179 mrc p15, 0, r0, c1, c0
1180 bic r0, r0, #0x000d
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1182 mov r0, #0
1183 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1184 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1189 mrc p15, 0, r0, c1, c0
1191 bic r0, r0, #0x0005
1193 bic r0, r0, #0x0004
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1196 mov r0, #0
1198 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1200 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1201 mcr p15, 0, r0, c7, c10, 4 @ DSB
1202 mcr p15, 0, r0, c7, c5, 4 @ ISB
1226 mov r3, #0
1227 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1230 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1232 bcs 2b @ entries 63 to 0
1234 bcs 1b @ segments 7 to 0
1236 teq r2, #0
1237 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1238 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1244 mov r1, #0
1245 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1246 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1247 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1251 mov r1, #0
1253 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1254 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1255 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1256 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1263 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1264 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1265 mov r10, #0
1267 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1275 0: cmp r0, r11 @ finished?
1277 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1279 b 0b
1281 mcr p15, 0, r10, c7, c10, 4 @ DSB
1282 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1283 mcr p15, 0, r10, c7, c10, 4 @ DSB
1284 mcr p15, 0, r10, c7, c5, 4 @ ISB
1290 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1292 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1301 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1325 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1326 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1327 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1334 mov r1, #0
1335 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1350 mov r2, #0
1359 add r2, r2, #'0'
1366 teq r2, #0
1369 mov r1, #0x00020000
1375 teq r0, #0
1382 mov r0, #0
1388 mov r11, #0
1435 mov r0, #0 @ must be 0
1446 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1447 bic r0, r0, #0x5 @ disable MMU and caches
1448 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1457 adr r1, 0f @ clean the region of code we
1476 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1477 tst r1, #0x1 @ MMU enabled at HYP?
1489 mcr p15, 4, r1, c1, c0, 0
1491 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1508 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1509 tst r0, #0x1 @ MMU enabled?
1517 adr r0, 0f @ switch to our stack
1521 mov r5, #0 @ appended DTB size
1522 mov r7, #0xFFFFFFFF @ machine ID
1525 0: .long .L_user_stack_end - .