44 	 * | snps,dw-apb-intc (MB)|  in axs10x_enable_gpio_intc_wire()
55 	 * DT hardware topology - connect MB intc directly to cpu intc  in axs10x_enable_gpio_intc_wire()
94 	char mb[32];  in axs10x_early_init()  local
104 	scnprintf(mb, 32, "MainBoard v%d", mb_rev);  in axs10x_early_init()
105 	axs10x_print_board_ver(CREG_MB_VER, mb);  in axs10x_early_init()
121  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
122  * of which maps to a corresponding 256MB aperture in Target slave memory map.
127  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131  * MB AXI Tunnel Master, which also has a mem map setup
133  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
134  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
148 /* MB AXI Target slaves */
155 /* MB AXI masters */
177 	{AXC001_SLV_AXI_TUNNEL,		0xE}, /* MB: CREG, CGU... */
182  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
183  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
205  * memmap for MB AXI Masters
206  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
223 	{AXS_MB_SLV_CONTROL,		0x0},	/* MB Local CREG, CGU... */
260 	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */  in axs101_early_init()
265 	/* MB peripherals memory map */  in axs101_early_init()
275 	/* Set up the MB interrupt system: mux interrupts to GPIO7) */  in axs101_early_init()
281 	/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */  in axs101_early_init()