Lines Matching +full:inter +full:- +full:processor

1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
29 #include <asm/processor.h>
49 return -EINVAL; in arc_get_cpu_map()
52 return -EINVAL; in arc_get_cpu_map()
59 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
65 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
66 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
81 * - Initialise the CPU possible map early - this describes the CPUs
83 * - Call early smp init hook. This can initialize a specific multi-core
112 * Default smp boot helper for Run-on-reset case where all cores start off
113 * together. Non-masters need to wait for Master to start running.
114 * This is implemented using a flag in memory, which Non-masters spin-wait on.
115 * Master sets it to cpu-id of core to "ungate" it.
140 /* for halt-on-reset, we've waited already */ in arc_platform_smp_wait_to_boot()
170 current->active_mm = mm; in start_kernel_secondary()
173 /* Some SMP H/w setup - for each cpu */ in start_kernel_secondary()
177 if (machine_desc->init_per_cpu) in start_kernel_secondary()
178 machine_desc->init_per_cpu(cpu); in start_kernel_secondary()
190 * Called from kernel_init( ) -> smp_init( ) - for each CPU
192 * At this point, Secondary Processor is "HALT"ed:
193 * -It booted, but was halted in head.S
194 * -It was configured to halt-on-reset
223 return -1; in __cpu_up()
232 /* Inter Processor Interrupt Handling */
243 * In arches with IRQ for each msg type (above), receiver can use IRQ-id to
245 * IRQ), the msg-type needs to be conveyed via per-cpu data
275 * so @new msg can be a free-loader in ipi_send_msg_one()
315 * ipi_cpu_stop - handle IPI from smp_send_stop()
347 * arch-common ISR to handle for inter-processor interrupts
381 * API called by platform code to hookup arch-common ISR to their IPI IRQ