Lines Matching +full:arc +full:- +full:timer

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
18  * -Platform independent, needed for each CPU (not foldable into init_IRQ)
19  * -Called very early (start_kernel -> setup_arch -> setup_processor)
22  * -Optionally, setup the High priority Interrupts as Level 2 IRQs
28        /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */  in arc_init_IRQ()
38 		pr_info("Level-2 interrupts bitset %x\n", level_mask);  in arc_init_IRQ()
54  * ARC700 core includes a simple on-chip intc supporting
55  * -per IRQ enable/disable
56  * -2 levels of interrupts (high/low)
57  * -all interrupts being level triggered
59  * To reduce platform code, we assume all IRQs directly hooked-up into intc.
60  * Platforms with external intc, hence cascaded IRQs, are free to over-ride
69 	ienb &= ~(1 << data->hwirq);  in arc_irq_mask()
78 	ienb |= (1 << data->hwirq);  in arc_irq_unmask()
83 	.name           = "ARC In-core Intc",
130 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
133  * arch_local_irq_enable - Enable interrupts.
135  * 1. Explicitly called to re-enable interrupts
141  * -If called from hard-ISR, it must not invert interrupt priorities
142  *  e.g. suppose TIMER is high priority (Level 2) IRQ
143  *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
144  *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
145  * -If called from soft-ISR, it must re-enable all interrupts
149  *    still we must re-enable both L1 and L2 IRQs
152  *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
153  *     over-written (this is deficiency in ARC700 Interrupt mechanism)