Lines Matching +full:designware +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
30 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <27000000>;
37 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
43 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <50000000>;
49 #clock-cells = <0>;
53 compatible = "fixed-clock";
61 clock-frequency = <25000000>;
62 #clock-cells = <0>;
67 compatible = "snps,axs10x-pgu-pll-clock";
69 #clock-cells = <0>;
74 #interrupt-cells = <1>;
78 interrupt-names = "macirq";
79 phy-mode = "rgmii";
81 snps,multicast-filter-bins = <256>;
83 clock-names = "stmmaceth";
84 max-speed = <100>;
86 reset-names = "stmmaceth";
87 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
91 compatible = "generic-ehci";
97 compatible = "generic-ohci";
109 * used through dw_mci_drv_data->prepare_command call-back.
110 * This call-back is used in Altera Socfpga platform and so
112 * "altr,socfpga-dw-mshc".
114 * Most probably "Hold Register" utilization is platform-
116 * "snps,dw-mshc" should be enough for all users of DW MMC once
121 compatible = "altr,socfpga-dw-mshc";
123 fifo-depth = < 16 >;
124 card-detect-delay = < 200 >;
126 clock-names = "biu", "ciu";
128 bus-width = < 4 >;
132 compatible = "snps,dw-apb-uart";
134 clock-frequency = <33333333>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
142 compatible = "snps,dw-apb-uart";
144 clock-frequency = <33333333>;
147 reg-shift = <2>;
148 reg-io-width = <4>;
153 compatible = "snps,dw-apb-uart";
155 clock-frequency = <33333333>;
158 reg-shift = <2>;
159 reg-io-width = <4>;
163 compatible = "snps,designware-i2c";
165 clock-frequency = <400000>;
170 i2s: i2s@1e000 { label
171 compatible = "snps,designware-i2s";
174 clock-names = "i2sclk";
176 #sound-dai-cells = <0>;
180 compatible = "snps,designware-i2c";
181 #address-cells = <1>;
182 #size-cells = <0>;
184 clock-frequency = <400000>;
192 adi,input-depth = <8>;
193 adi,input-colorspace = "rgb";
194 adi,input-clock = "1x";
195 adi,clock-delay = <0x03>;
196 #sound-dai-cells = <0>;
199 #address-cells = <1>;
200 #size-cells = <0>;
206 remote-endpoint = <&pgu_output>;
214 remote-endpoint = <&hdmi_connector_in>;
234 compatible = "hdmi-connector";
238 remote-endpoint = <&adv7511_output>;
244 compatible = "snps,dw-apb-gpio";
246 #address-cells = <1>;
247 #size-cells = <0>;
249 gpio0_banka: gpio-controller@0 {
250 compatible = "snps,dw-apb-gpio-port";
251 gpio-controller;
252 #gpio-cells = <2>;
253 snps,nr-gpios = <32>;
257 gpio0_bankb: gpio-controller@1 {
258 compatible = "snps,dw-apb-gpio-port";
259 gpio-controller;
260 #gpio-cells = <2>;
261 snps,nr-gpios = <8>;
265 gpio0_bankc: gpio-controller@2 {
266 compatible = "snps,dw-apb-gpio-port";
267 gpio-controller;
268 #gpio-cells = <2>;
269 snps,nr-gpios = <8>;
275 compatible = "snps,dw-apb-gpio";
277 #address-cells = <1>;
278 #size-cells = <0>;
280 gpio1_banka: gpio-controller@0 {
281 compatible = "snps,dw-apb-gpio-port";
282 gpio-controller;
283 #gpio-cells = <2>;
284 snps,nr-gpios = <30>;
288 gpio1_bankb: gpio-controller@1 {
289 compatible = "snps,dw-apb-gpio-port";
290 gpio-controller;
291 #gpio-cells = <2>;
292 snps,nr-gpios = <10>;
296 gpio1_bankc: gpio-controller@2 {
297 compatible = "snps,dw-apb-gpio-port";
298 gpio-controller;
299 #gpio-cells = <2>;
300 snps,nr-gpios = <8>;
309 clock-names = "pxlclk";
310 memory-region = <&frame_buffer>;
313 remote-endpoint = <&adv7511_input>;
319 compatible = "simple-audio-card";
320 simple-audio-card,name = "AXS10x HDMI Audio";
321 simple-audio-card,format = "i2s";
322 simple-audio-card,cpu {
323 sound-dai = <&i2s>;
325 simple-audio-card,codec {
326 sound-dai = <&adv7511>;