Lines Matching full:e0
34 insbl $17,1,$17 /* .. E0 */
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
45 addq $18,$16,$6 /* E0 */
47 xor $16,$6,$1 /* E0 */
50 bic $1,7,$1 /* E0 */
52 and $16,7,$3 /* E0 */
55 ldq_u $4,0($16) /* E0 */
57 insql $17,$16,$2 /* E0 */
60 addq $18,$3,$18 /* E0 $18 is new count ($3 is negative) */
62 subq $16,$3,$16 /* E0 $16 is new aligned destination */
65 bis $31,$31,$31 /* E0 */
67 stq_u $1,0($5) /* E0 */
72 sra $18,3,$3 /* E0 */
74 bis $16,$16,$5 /* E0 */
79 stq $17,0($5) /* E0 */
81 addq $5,8,$5 /* E0 */
85 bis $31,$31,$31 /* E0 */
87 ldq $7,0($5) /* E0 */
90 insqh $17,$6,$4 /* E0 */
92 stq $1,0($5) /* E0 */
97 ldq_u $1,0($16) /* E0 */
99 mskql $1,$16,$4 /* E0 (after load stall) */
100 bis $2,$4,$2 /* E0 */
102 mskql $2,$6,$4 /* E0 */
104 bis $2,$4,$1 /* E0 */
105 stq_u $1,0($16) /* E0 */
118 inswl $17,0,$1 /* E0 */
119 inswl $17,2,$2 /* E0 */
120 inswl $17,4,$3 /* E0 */
122 inswl $17,6,$4 /* E0 */
124 or $1,$4,$17 /* E0 */