Lines Matching +full:cycle +full:- +full:0

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-csum_ipv6_magic.S
4  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17  *	E	- either cluster
18  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
29  * Swap <proto> (takes form 0xaabb)
31  *	0xbbaa0000 00000000
32  * Then turn it back into a sign extended 32-bit item
33  *	0xbbaa0000
35  * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36  * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
37  * Assume input takes form 0xAABBCCDD
41  * add carry bits + ushort --> ushort
42  * add carry bits + ushort --> ushort (in case the carry results in an overflow)
53  * may cause additional delay in rare cases (load-load replay traps).
60 	.frame $30,0,$26,0
62 	.prologue 0
64 	ldq_u	$0,0($16)	# L : Latency: 3
67 	sll	$19,8,$7	# U : U L U L : 0x00000000 00aabb00
72 	ldq_u	$2,0($17)	# L : U L U L : Latency: 3
74 	extql	$0,$6,$0	# U :
77 	sll	$19,24,$19	# U : U U L U : 0x000000aa bb000000
84 	or	$0,$22,$0	# E : 1st src word complete
96 	addq	$20,$0,$20	# E : begin summing the words
101 	zap	$19,0x3,$19	# U : <sign bits>bbaa0000
104 	cmpult	$20,$0,$0	# E :
106 	zapnot	$18,0xa,$18	# U : 00000000DD00BB00
107 	zap	$4,0xa,$4	# U : U U L L : 0000000000CC00AA
116 	cmpult	$20,$3,$3	# E : (1 cycle stall on $20)
117 	addq	$20,$18,$20	# E : U L U L (1 cycle stall on $20)
120 	addq	$20,$19,$20	# E : (1 cycle stall on $20)
121 	addq	$0,$1,$0	# E : merge the carries back into the csum
125 	addq	$18,$19,$18	# E : (1 cycle stall on $19)
126 	addq	$0,$2,$0	# E :
128 		/* (1 cycle stall on $18, 2 cycles on $20) */
130 	addq	$0,$20,$0	# E :
131 	zapnot	$0,15,$1	# U : Start folding output (1 cycle stall on $0)
133 	srl	$0,32,$0	# U : U L U L : (1 cycle stall on $0)
135 	addq	$1,$0,$1	# E : Finished generating ulong
136 	extwl	$1,2,$2		# U : ushort[1] (1 cycle stall on $1)
137 	zapnot	$1,3,$0		# U : ushort[0] (1 cycle stall on $1)
138 	extwl	$1,4,$1		# U : ushort[2] (1 cycle stall on $1)
140 	addq	$0,$2,$0	# E
141 	addq	$0,$1,$3	# E : Finished generating uint
142 		/* (1 cycle stall on $0) */
143 	extwl	$3,2,$1		# U : ushort[1] (1 cycle stall on $3)
146 	addq	$1,$3,$0	# E : Final carry
147 	not	$0,$4		# E : complement (1 cycle stall on $0)
148 	zapnot	$4,3,$0		# U : clear upper garbage bits
149 		/* (1 cycle stall on $4) */