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1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
41 * add carry bits + ushort --> ushort
42 * add carry bits + ushort --> ushort (in case the carry results in an overflow)
53 * may cause additional delay in rare cases (load-load replay traps).
71 zapnot $20,15,$20 # U : zero extend incoming csum
96 addq $20,$0,$20 # E : begin summing the words
104 cmpult $20,$0,$0 # E :
105 addq $20,$1,$20 # E :
111 cmpult $20,$1,$1 # E :
112 addq $20,$2,$20 # E : U L U L
114 cmpult $20,$2,$2 # E :
115 addq $20,$3,$20 # E :
116 cmpult $20,$3,$3 # E : (1 cycle stall on $20)
117 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20)
119 cmpult $20,$18,$18 # E :
120 addq $20,$19,$20 # E : (1 cycle stall on $20)
124 cmpult $20,$19,$19 # E :
127 addq $20,$18,$20 # E : U L U L :
128 /* (1 cycle stall on $18, 2 cycles on $20) */
130 addq $0,$20,$0 # E :