1 // SPDX-License-Identifier: GPL-2.0
39 	irq = (vector - 0x800) >> 4;  in miata_srm_device_interrupt()
47 	 *  for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't  in miata_srm_device_interrupt()
49 	 *  vectors 0x800-0x8f0).  in miata_srm_device_interrupt()
53 	 * So, here's this grotty hack... :-(  in miata_srm_device_interrupt()
83 	if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL))  in miata_init_irq()
84 		pr_err("Failed to register halt-switch interrupt\n");  in miata_init_irq()
85 	if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL))  in miata_init_irq()
86 		pr_err("Failed to register timer-cascade interrupt\n");  in miata_init_irq()
97  * 2        Halt/Reset switch
102  * 7        PCI-ISA Bridge
119  *24        Interrupt Line A from slot 2
120  *25        Interrupt Line B from slot 2
121  *26        Interrupt Line C from slot 2
122  *27        Interrupt Line D from slot 2
135  *  7       PCI-ISA bridge
136  *  8       PCI-PCI Bridge      (SBU Riser)
145  * 14       PCI on board slot 2 (SBU Riser)
149  * This two layered interrupt approach means that we allocate IRQ 16 and 
160 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 15,  EIDE    */  in miata_map_irq()
161 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 16,  none    */  in miata_map_irq()
162 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 17,  none    */  in miata_map_irq()
163 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCI-ISA */  in miata_map_irq()
164 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PCI-PCI */  in miata_map_irq()
165 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  none    */  in miata_map_irq()
166 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  none    */  in miata_map_irq()
171 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 25,  none    */  in miata_map_irq()
172 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 26,  none    */  in miata_map_irq()
173 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 27,  none    */  in miata_map_irq()
175 		{16+24, 16+24, 16+25, 16+26, 16+27},  /* IdSel 29,  slot 2  */  in miata_map_irq()
178 		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 31,  PCI-PCI */  in miata_map_irq()
183            the 2nd 8259 controller. So we have to check for it first. */  in miata_map_irq()
185 	if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) {  in miata_map_irq()
186 		struct pci_dev *pdev = pci_get_slot(dev->bus, dev->devfn & ~7);  in miata_map_irq()
191 			return -1;  in miata_map_irq()
196 		return ret == PCIBIOS_SUCCESSFUL ? irq : -1;  in miata_map_irq()
207 	if (dev->bus->number == 0) {  in miata_swizzle()
208 		slot = PCI_SLOT(dev->devfn);  in miata_swizzle()
210 	/* Check for the built-in bridge.  */  in miata_swizzle()
211 	else if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||  in miata_swizzle()
212 		 (PCI_SLOT(dev->bus->self->devfn) == 20)) {  in miata_swizzle()
213 		slot = PCI_SLOT(dev->devfn) + 9;  in miata_swizzle()
217 		/* Must be a card-based bridge.  */  in miata_swizzle()
219 			if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||  in miata_swizzle()
220 			    (PCI_SLOT(dev->bus->self->devfn) == 20)) {  in miata_swizzle()
221 				slot = PCI_SLOT(dev->devfn) + 9;  in miata_swizzle()
227 			dev = dev->bus->self;  in miata_swizzle()
229 			slot = PCI_SLOT(dev->devfn);  in miata_swizzle()
230 		} while (dev->bus->self);  in miata_swizzle()
252 		/* Who said DEC engineers have no sense of humor? ;-)  */   in miata_kill_arch()