48 #define DEBUG_CONFIG 0
71  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
73  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
99 	DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "  in mk_conf_addr()
100 		 "pci_addr=0x%p, type1=0x%p)\n",  in mk_conf_addr()
104 		bus = 0;  in mk_conf_addr()
105 	*type1 = (bus != 0);  in mk_conf_addr()
111 	DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));  in mk_conf_addr()
112 	return 0;  in mk_conf_addr()
187 	if (((start ^ end) & 0xffff0000) == 0)  in tsunami_pci_tbi()
192 	value = (start & 0xffff0000) >> 12;  in tsunami_pci_tbi()
207 	mcheck_taken(cpu) = 0;  in tsunami_probe_read()
212 	mcheck_expected(cpu) = 0;  in tsunami_probe_read()
214 	mcheck_taken(cpu) = 0;  in tsunami_probe_read()
217 	printk("dont_care == 0x%lx\n", dont_care);  in tsunami_probe_read()
229 	*vaddr = 0;  in tsunami_probe_write()
234 		probe_result = 0;  in tsunami_probe_write()
235 		printk("tsunami_probe_write: unit %d at 0x%016lx\n", source,  in tsunami_probe_write()
251 	if (tsunami_probe_read(&pchip->pctl.csr) == 0)  in tsunami_init_one_pchip()
255 	if (index == 0)  in tsunami_init_one_pchip()
264 	hose->sparse_mem_base = 0;  in tsunami_init_one_pchip()
265 	hose->sparse_io_base = 0;  in tsunami_init_one_pchip()
267 	  = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L;  in tsunami_init_one_pchip()
269 	  = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L;  in tsunami_init_one_pchip()
280 	hose->mem_space->end = hose->mem_space->start + 0xffffffff;  in tsunami_init_one_pchip()
284 	if (request_resource(&ioport_resource, hose->io_space) < 0)  in tsunami_init_one_pchip()
286 	if (request_resource(&iomem_resource, hose->mem_space) < 0)  in tsunami_init_one_pchip()
294 	saved_config[index].wsba[0] = pchip->wsba[0].csr;  in tsunami_init_one_pchip()
295 	saved_config[index].wsm[0] = pchip->wsm[0].csr;  in tsunami_init_one_pchip()
296 	saved_config[index].tba[0] = pchip->tba[0].csr;  in tsunami_init_one_pchip()
315 	 * Window 0 is scatter-gather 8MB at 8MB (for isa)  in tsunami_init_one_pchip()
322 	hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000,  in tsunami_init_one_pchip()
327 	hose->sg_pci = iommu_arena_new(hose, 0x40000000,  in tsunami_init_one_pchip()
328 				       size_for_memory(0x40000000),  in tsunami_init_one_pchip()
332 	__direct_map_base = 0x80000000;  in tsunami_init_one_pchip()
333 	__direct_map_size = 0x80000000;  in tsunami_init_one_pchip()
335 	pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;  in tsunami_init_one_pchip()
336 	pchip->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;  in tsunami_init_one_pchip()
337 	pchip->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);  in tsunami_init_one_pchip()
340 	pchip->wsm[1].csr  = (hose->sg_pci->size - 1) & 0xfff00000;  in tsunami_init_one_pchip()
343 	pchip->wsba[2].csr = 0x80000000 | 1;  in tsunami_init_one_pchip()
344 	pchip->wsm[2].csr  = (0x80000000 - 1) & 0xfff00000;  in tsunami_init_one_pchip()
345 	pchip->tba[2].csr  = 0;  in tsunami_init_one_pchip()
347 	pchip->wsba[3].csr = 0;  in tsunami_init_one_pchip()
352 	tsunami_pci_tbi(hose, 0, -1);  in tsunami_init_one_pchip()
383 	wrent(entInt, 0);  in tsunami_init_arch()
388 	printk("%s: probing bogus address:  0x%016lx\n", __func__, bogus_addr);  in tsunami_init_arch()
394 #if 0  in tsunami_init_arch()
396 	printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);  in tsunami_init_arch()
397 	printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);  in tsunami_init_arch()
398 	printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);  in tsunami_init_arch()
399 	printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);  in tsunami_init_arch()
400 	printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);  in tsunami_init_arch()
401 	printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);  in tsunami_init_arch()
402 	printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);  in tsunami_init_arch()
403 	printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);  in tsunami_init_arch()
406 	printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);  in tsunami_init_arch()
407 	printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);  in tsunami_init_arch()
408 	printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);  in tsunami_init_arch()
411 	ioport_resource.end = ~0UL;  in tsunami_init_arch()
416 	tsunami_init_one_pchip(TSUNAMI_pchip0, 0);  in tsunami_init_arch()
427 	pchip->wsba[0].csr = saved_config[index].wsba[0];  in tsunami_kill_one_pchip()
428 	pchip->wsm[0].csr = saved_config[index].wsm[0];  in tsunami_kill_one_pchip()
429 	pchip->tba[0].csr = saved_config[index].tba[0];  in tsunami_kill_one_pchip()
447 	tsunami_kill_one_pchip(TSUNAMI_pchip0, 0);  in tsunami_kill_arch()
456 	pchip->perror.csr = 0x040;  in tsunami_pci_clr_err_1()
479 	wrmces(0x7);  in tsunami_machine_check()