207 	volatile unsigned long *csr;  in titan_pci_tbi()  local
220 	csr = &port->port_specific.g.gtlbia.csr;  in titan_pci_tbi()
222 		csr = &port->port_specific.g.gtlbiv.csr;  in titan_pci_tbi()
229 	*csr = value;  in titan_pci_tbi()
231 	*csr;  in titan_pci_tbi()
240 	pctl.pctl_q_whole = port->pctl.csr;  in titan_query_agp()
293 	saved_config[index].wsba[0] = port->wsba[0].csr;  in titan_init_one_pachip_port()
294 	saved_config[index].wsm[0]  = port->wsm[0].csr;  in titan_init_one_pachip_port()
295 	saved_config[index].tba[0]  = port->tba[0].csr;  in titan_init_one_pachip_port()
297 	saved_config[index].wsba[1] = port->wsba[1].csr;  in titan_init_one_pachip_port()
298 	saved_config[index].wsm[1]  = port->wsm[1].csr;  in titan_init_one_pachip_port()
299 	saved_config[index].tba[1]  = port->tba[1].csr;  in titan_init_one_pachip_port()
301 	saved_config[index].wsba[2] = port->wsba[2].csr;  in titan_init_one_pachip_port()
302 	saved_config[index].wsm[2]  = port->wsm[2].csr;  in titan_init_one_pachip_port()
303 	saved_config[index].tba[2]  = port->tba[2].csr;  in titan_init_one_pachip_port()
305 	saved_config[index].wsba[3] = port->wsba[3].csr;  in titan_init_one_pachip_port()
306 	saved_config[index].wsm[3]  = port->wsm[3].csr;  in titan_init_one_pachip_port()
307 	saved_config[index].tba[3]  = port->tba[3].csr;  in titan_init_one_pachip_port()
326 	port->wsba[0].csr = hose->sg_isa->dma_base | 3;  in titan_init_one_pachip_port()
327 	port->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;  in titan_init_one_pachip_port()
328 	port->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);  in titan_init_one_pachip_port()
330 	port->wsba[1].csr = __direct_map_base | 1;  in titan_init_one_pachip_port()
331 	port->wsm[1].csr  = (__direct_map_size - 1) & 0xfff00000;  in titan_init_one_pachip_port()
332 	port->tba[1].csr  = 0;  in titan_init_one_pachip_port()
334 	port->wsba[2].csr = hose->sg_pci->dma_base | 3;  in titan_init_one_pachip_port()
335 	port->wsm[2].csr  = (hose->sg_pci->size - 1) & 0xfff00000;  in titan_init_one_pachip_port()
336 	port->tba[2].csr  = virt_to_phys(hose->sg_pci->ptes);  in titan_init_one_pachip_port()
338 	port->wsba[3].csr = 0;  in titan_init_one_pachip_port()
341 	port->pctl.csr |= pctl_m_mwin;  in titan_init_one_pachip_port()
347 		port->port_specific.a.agplastwr.csr = __direct_map_base;  in titan_init_one_pachip_port()
355 	titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;  in titan_init_pachips()
372 	printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr);  in titan_init_arch()
373 	printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr);  in titan_init_arch()
374 	printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr);  in titan_init_arch()
375 	printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);  in titan_init_arch()
376 	printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);  in titan_init_arch()
377 	printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);  in titan_init_arch()
378 	printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr);  in titan_init_arch()
379 	printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr);  in titan_init_arch()
382 	printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);  in titan_init_arch()
383 	printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr);  in titan_init_arch()
384 	printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr);  in titan_init_arch()
407 	port->wsba[0].csr = saved_config[index].wsba[0];  in titan_kill_one_pachip_port()
408 	port->wsm[0].csr  = saved_config[index].wsm[0];  in titan_kill_one_pachip_port()
409 	port->tba[0].csr  = saved_config[index].tba[0];  in titan_kill_one_pachip_port()
411 	port->wsba[1].csr = saved_config[index].wsba[1];  in titan_kill_one_pachip_port()
412 	port->wsm[1].csr  = saved_config[index].wsm[1];  in titan_kill_one_pachip_port()
413 	port->tba[1].csr  = saved_config[index].tba[1];  in titan_kill_one_pachip_port()
415 	port->wsba[2].csr = saved_config[index].wsba[2];  in titan_kill_one_pachip_port()
416 	port->wsm[2].csr  = saved_config[index].wsm[2];  in titan_kill_one_pachip_port()
417 	port->tba[2].csr  = saved_config[index].tba[2];  in titan_kill_one_pachip_port()
419 	port->wsba[3].csr = saved_config[index].wsba[3];  in titan_kill_one_pachip_port()
420 	port->wsm[3].csr  = saved_config[index].wsm[3];  in titan_kill_one_pachip_port()
421 	port->tba[3].csr  = saved_config[index].tba[3];  in titan_kill_one_pachip_port()
645 	pctl.pctl_q_whole = port->pctl.csr;  in titan_agp_configure()
674 	port->pctl.csr = pctl.pctl_q_whole;  in titan_agp_configure()
794 	pctl.pctl_q_whole = port->pctl.csr;  in titan_agp_info()