Lines Matching +full:system +full:- +full:clock +full:- +full:frequency
1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
38 KVM clock are special enough to warrant a full exposition and are described in
41 2.1. i8254 - PIT
42 ----------------
45 or PIT. The PIT has a fixed frequency 1.193182 MHz base clock and three
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
62 | Clock | | | |
63 -------------- | +->| GATE TIMER 0 |
64 | ----------------
66 | ----------------
68 |------>| CLOCK OUT | ---------> 66.3 KHZ DRAM
70 | +->| GATE TIMER 1 |
71 | ----------------
73 | ----------------
75 |------>| CLOCK OUT | ---------> Port 61h, bit 5
77 Port 61h, bit 0 -------->| GATE TIMER 2 | \_.---- ____
78 ---------------- _| )--|LPF|---Speaker
79 / *---- \___/
80 Port 61h, bit 1 ---------------------------------/
85 This is a one-shot software timeout that counts down
89 Mode 1: Triggered One-shot.
107 each clock to generate a full high / low cycle at the full periodic rate.
108 If the count is even, the clock remains high for N/2 counts and low for N/2
109 counts; if the clock is odd, the clock is high for (N+1)/2 counts and low
110 for (N-1)/2 counts. Only even values are latched by the counter, so odd
112 which generates sine-like tones by low-pass filtering the square wave output.
117 goes low for 1 clock cycle and returns high. The counter is not reloaded.
124 the output goes low for 1 clock cycle and then returns high. The counter is
133 Bit 7-4: Command (See table below)
134 Bit 3-1: Mode (000 = Mode 0, 101 = Mode 5, 11X = undefined)
139 0000 - Latch Timer 0 count for port 0x40
144 0001 - Set Timer 0 LSB mode for port 0x40
148 0010 - Set Timer 0 MSB mode for port 0x40
152 0011 - Set Timer 0 16-bit mode for port 0x40
156 0100 - Latch Timer 1 count for port 0x41 - as described above
157 0101 - Set Timer 1 LSB mode for port 0x41 - as described above
158 0110 - Set Timer 1 MSB mode for port 0x41 - as described above
159 0111 - Set Timer 1 16-bit mode for port 0x41 - as described above
161 1000 - Latch Timer 2 count for port 0x42 - as described above
162 1001 - Set Timer 2 LSB mode for port 0x42 - as described above
163 1010 - Set Timer 2 MSB mode for port 0x42 - as described above
164 1011 - Set Timer 2 16-bit mode for port 0x42 as described above
166 1101 - General counter latch
173 1110 - Latch timer status
179 The output of ports 0x40-0x42 following this command will be:
183 Bit 5-4 = Read / Write mode
186 11 = LSB / MSB (16-bit)
187 Bit 3-1 = Mode
191 --------
194 time clock. The original device is now obsolete, and usually emulated by the
195 system chipset, sometimes by an HPET and some frankenstein IRQ routing.
209 system is off. The current time fields should not be read while an update is
212 The clock uses a 32.768kHz crystal, so bits 6-4 of register A should be
218 ------------------------------------------
231 bit 6-4 = Divider for clock
238 bit 3-0 = Rate selection for periodic interrupt
252 bit 4 = Update-ended interrupt enable
255 bit 1 = 12-hour mode (0) / 24-hour mode (1)
262 bit 3-0 = reserved
265 bit 6-0 = reserved
270 ---------
272 On Pentium and later processors, an on-board timer is available to each CPU
274 accessed through memory-mapped registers and provides interrupt service to each
279 the APIC CPU-local memory-mapped hardware. Beware that CPU errata may affect
281 these workarounds pose unique constraints for virtualization - requiring either
282 extra overhead incurred from extra reads of memory-mapped I/O or additional
288 of one-shot or periodic operation, and is based on the bus clock divided down
292 ---------
302 fixed rate on the timer frequency, but does impose some extremal values on
303 frequency, error and slew.
307 in any given system). The HPET is also memory-mapped, and its presence is
314 --------------------
322 not considered important at this time as no known operating system does this.
332 The TSC is represented internally as a 64-bit MSR which can be read with the
335 was only possible to write the low 32-bits of the 64-bit counter, and the upper
336 32-bits of the counter were cleared. Now, however, on Intel processors family
338 has been lifted and all 64-bits are writable. On AMD systems, the ability to
341 The TSC is accessible from CPL-0 and conditionally, for CPL > 0 software by
357 ------------------------
359 The TSC is a CPU-local clock in most implementations. This means, on SMP
362 the same clock, however, this is not always the case.
365 the operating system or other system software may attempt to do this as well.
366 Several hardware limitations make the problem worse - if it is not possible to
367 write the full 64-bits of the TSC, it may be impossible to match the TSC in
368 newly arriving CPUs to that of the rest of the system, resulting in
369 unsynchronized TSCs. This may be done by BIOS or system software, but in
371 values are read from the same clock, which generally only is possible on single
375 ------------------------
377 As touched on already, CPUs which arrive later than the boot time of the system
378 may not have a TSC value that is synchronized with the rest of the system.
379 Either system software, BIOS, or SMM code may actually try to establish the TSC
380 to a value matching the rest of the system, but a perfect match is usually not
381 a guarantee. This can have the effect of bringing a system from a state where
385 3.3. TSC and multi-socket / NUMA
386 --------------------------------
388 Multi-socket systems, especially large multi-socket systems are likely to have
389 individual clocksources rather than a single, universally distributed clock.
391 perfectly matched frequency, and temperature and electrical variations will
393 exact clock and bus design, the drift may or may not be fixed in absolute
397 cores. This technique, known as spread-spectrum clocking, reduces EMI at the
398 clock frequency and harmonics of it, which may be required to pass FCC
404 3.4. TSC and C-states
405 ---------------------
407 C-states, or idling states of the processor, especially C1E and deeper sleep
410 is resumed. Such CPUs must be detected and flagged by the operating system
416 3.5. TSC frequency change / P-states
417 ------------------------------------
419 To make things slightly more interesting, some CPUs may change frequency. They
420 may or may not run the TSC at the same rate, and because the frequency change
424 external clock to be a usable source of time.
426 Whether the TSC runs at a constant rate or scales with the P-state is model
430 In addition, some vendors have known bugs where the P-state is actually
432 inactive, the P-state may be raised temporarily to service cache misses from
434 than that of non-halted processors. AMD Turion processors are known to have
437 3.6. TSC and STPCLK / T-states
438 ------------------------------
445 3.7. TSC virtualization - VMX
446 -----------------------------
454 3.8. TSC virtualization - SVM
455 -----------------------------
463 ------------------------------
467 if so, the TSCs in multi-sockets or NUMA systems may still run independently
476 X86_FEATURE_CONSTANT_TSC The TSC rate is unchanged with P-states
477 X86_FEATURE_NONSTOP_TSC The TSC does not stop in C-states
487 operating system does not run with 100% usage of the CPU, despite the fact that
492 of machine interrupts and the associated clock sources are no longer completely
502 -----------------------
505 is that the system timekeeping routines are often designed to keep track of
515 'wall clock' or 'real time' may not need any adjustment of their interrupts to
532 -----------------------------------
543 non-serialized. Forcing serialized execution is necessary for precise
552 system.
555 ----------------------
560 while another clock is still expressing the same value.
562 That is, you may read (T,T+10) while external clock C maintains the same value.
563 Due to non-serialized reads, you may actually end up with a range which
564 fluctuates - from (T-1.. T+10). Thus, any time calculated from a TSC, but
566 Re-calibrating this computation may actually cause time, as computed after the
572 timespec - but which advances in much larger granularity intervals, sometimes
580 --------------
585 be able to help to some degree here, as the clock correction required is
586 typically small enough to fall in the NTP-correctable window.
589 clock is exposed) may now be running at different rates, requiring compensation
592 faster clock cannot be made visible to a guest without the potential of time
593 advancing faster than usual. A slower clock is less of a problem, as it can
594 always be caught up to the original rate. KVM clock avoids these problems by
599 ---------------
602 scheduling algorithms of an operating system may be adversely affected by
609 paravirtualized scheduler clock, which reveals the true amount of CPU time for
613 --------------
622 --------------------------------
624 Precise timing and delays may not be possible in a virtualized system. This
625 can happen if the system is controlling physical hardware, or issues delays to
627 in general for a virtualized system; hardware control software can't be
628 adequately virtualized without a full real-time operating system, which would
636 ------------------------------
641 red-pill type detection), and it may allow information to leak between guests
645 but in general isn't recommended for real-world deployment scenarios.