Lines Matching full:may

31 timekeeping which may be difficult to find elsewhere, specifically,
279 the APIC CPU-local memory-mapped hardware.  Beware that CPU errata may affect
280 the use of the APIC and that workarounds may be required.  In addition, some of
283 functionality that may be more computationally expensive to implement.
297 systems designated as legacy free may support only the HPET as a hardware timer
317 timing chips built into the cards which may have registers which are accessible
360 platforms, the TSCs of different CPUs may start at different times depending
364 The BIOS may attempt to resynchronize the TSCs during the poweron process and
365 the operating system or other system software may attempt to do this as well.
367 write the full 64-bits of the TSC, it may be impossible to match the TSC in
369 unsynchronized TSCs.  This may be done by BIOS or system software, but in
378 may not have a TSC value that is synchronized with the rest of the system.
379 Either system software, BIOS, or SMM code may actually try to establish the TSC
383 small, may be exposed to the OS and any virtualization environment.
393 exact clock and bus design, the drift may or may not be fixed in absolute
394 error, and may accumulate over time.
396 In addition, very large systems may deliberately slew the clocks of individual
398 clock frequency and harmonics of it, which may be required to pass FCC
408 states may be problematic for TSC as well.  The TSC may stop advancing in such
413 The TSC in such a case may be corrected by catching it up to a known external
419 To make things slightly more interesting, some CPUs may change frequency.  They
420 may or may not run the TSC at the same rate, and because the frequency change
421 may be staggered or slewed, at some points in time, the TSC rate may not be
432 inactive, the P-state may be raised temporarily to service cache misses from
440 External signals given to the processor may also have the effect of stopping
467 if so, the TSCs in multi-sockets or NUMA systems may still run independently
488 it may very well make that assumption.  It may expect it to remain true to very
490 virtual interrupt sources are disabled, and the machine may still be preempted
495 This same problem can occur on native hardware to a degree, as SMM mode may
497 BIOS, but not in such an extreme fashion.  However, the fact that SMM mode may
506 time by counting periodic interrupts.  These interrupts may come from the PIT
507 or the RTC, but the problem is the same: the host virtualization engine may not
509 time may fall behind.  This is especially problematic if a high interrupt rate
513 There are three approaches to solving this problem; first, it may be possible
515 'wall clock' or 'real time' may not need any adjustment of their interrupts to
516 maintain proper time.  If this is not sufficient, it may be necessary to inject
520 solution to the problem has risen: the guest may need to become aware of lost
542 which may execute instructions out of order.  Such execution is called
547 Since CPUID may actually be virtualized by a trap and emulate mechanism, this
549 accurate time stamp counter reading may therefore not always be available, and
550 it may be necessary for an implementation to guard against "backwards" reads of
559 the TSC is much higher precision, many possible values of the TSC may be read
562 That is, you may read (T,T+10) while external clock C maintains the same value.
563 Due to non-serialized reads, you may actually end up with a range which
565 calibrated against an external value may have a range of valid values.
566 Re-calibrating this computation may actually cause time, as computed after the
583 First, the migration itself may take time, during which interrupts cannot be
584 delivered, and after which, the guest time may need to be caught up.  NTP may
589 clock is exposed) may now be running at different rates, requiring compensation
591 migrating to a faster machine may preclude the use of a passthrough TSC, as a
601 Since scheduling may be based on precise timing and firing of interrupts, the
602 scheduling algorithms of an operating system may be adversely affected by
605 causes of virtualization exits, possible context switch), this may not always
615 Watchdog timers, such as the lock detector in Linux may fire accidentally when
618 spurious and can be ignored, but in some circumstances it may be necessary to
624 Precise timing and delays may not be possible in a virtualized system.  This
631 The second issue may cause performance problems, but this is unlikely to be a
632 significant issue.  In many cases these delays may be eliminated through
640 time.  This may allow the guest to infer the presence of a hypervisor (as in a
641 red-pill type detection), and it may allow information to leak between guests
643 problems would require completely isolated virtual time which may not track
644 real time any longer.  This may be useful in certain security or QA contexts,