Lines Matching +full:data +full:- +full:ready
1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
23 data:
24 4-byte alignment physical address of a memory area which must be
34 whose data will be filled in by the hypervisor. The hypervisor is only
35 guaranteed to update this data at the moment of MSR write.
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
62 data:
63 4-byte aligned physical address of a memory area which must be in
78 whose data will be filled in by the hypervisor periodically. Only one
80 updates of this structure is arbitrary and implementation-dependent.
89 An odd version indicates an in-progress update.
104 tsc-related quantity to nanoseconds
107 shift to be used when converting tsc-related
115 derive per-CPU time by doing::
117 time = (current_tsc - tsc_timestamp)
121 time >>= -tsc_shift;
132 +-----------+--------------+----------------------------------+
134 +-----------+--------------+----------------------------------+
138 +-----------+--------------+----------------------------------+
142 +-----------+--------------+----------------------------------+
151 data and functioning:
163 data and functioning:
192 data:
195 Bits 63-6 hold 64-byte aligned physical address of a 64 byte memory area
203 /* Used for 'page ready' events delivered via interrupt notification */
209 Bits 5-4 of the MSR are reserved and should be zero. Bit 0 is set to 1
214 present in CPUID. Bit 3 enables interrupt based delivery of 'page ready'
234 Bytes 4-7 of 64 byte memory location ('token') will be written to by the
235 hypervisor at the time of APF 'page ready' event injection. The content
239 'page ready' event and to write '1' to MSR_KVM_ASYNC_PF_ACK after
240 clearing the location; writing to the MSR forces KVM to re-scan its
244 ready' APF delivery needs to be written to before enabling APF mechanism
248 Note, previously, 'page ready' events were delivered via the same #PF
255 Currently 'page ready' APF events will be always delivered on the
262 data:
263 64-byte alignment physical address of a memory area which must be
276 whose data will be filled in by the hypervisor periodically. Only one
278 updates of this structure is arbitrary and implementation-dependent.
289 in-progress update.
302 not. Non-zero values mean the vCPU has been preempted. Zero
309 data:
312 interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned
320 EOI by clearing the bit in guest memory - this location will
345 Control host-side polling.
347 data:
348 Bit 0 enables (1) or disables (0) host-side HLT polling logic.
356 data:
359 Bits 0-7: APIC vector for delivery of 'page ready' APF events.
360 Bits 8-63: Reserved
362 Interrupt vector for asynchnonous 'page ready' notifications delivery.
370 data:
373 When the guest is done processing 'page ready' APF event and 'token'
375 write '1' to bit 0 of the MSR, this causes the host to re-scan its queue
382 data: