Lines Matching full:debug
2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
14 external debug. Usually the external debug mode is well known as the external
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
22 debug mechanism, Linux kernel can access these related registers from mmio
36 - At the time this documentation was written, the debug driver mainly relies on
69 Before accessing debug registers, we should ensure the clock and power domain
71 Debug registers', the debug registers are spread into two domains: the debug
80 | Debug |**| CPU |
87 For debug domain, the user uses DT binding "clocks" and "power-domains" to
88 specify the corresponding clock source and power supply for the debug logic.
90 debug power domain.
93 schemes and finally this heavily impacts external debug module. So we can
101 powered on properly during the period when access debug related registers;
104 are powered down - including the parts of the debug registers that should
105 remain powered in the debug power domain. The bits in EDPRCR are not
106 respected in these cases, so these designs do not support debug over
107 power down in the way that the CoreSight / Debug designers anticipated.
111 In this case, accessing to the debug registers while they are not powered
120 See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for
133 # insmod coresight_cpu_debug.ko debug=1
139 To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable::
141 # echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
143 To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable::
145 # echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable
148 platform which has idle states to power off debug logic and the power
151 ensure the accessing to debug logic.
183 ARM external debug module:
184 coresight-cpu-debug 850000.debug: CPU[0]:
185 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
186 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
187 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
188 …coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
189 coresight-cpu-debug 852000.debug: CPU[1]:
190 coresight-cpu-debug 852000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
191 coresight-cpu-debug 852000.debug: EDPCSR: debug_notifier_call+0x23c/0x358
192 coresight-cpu-debug 852000.debug: EDCIDSR: 00000000
193 …coresight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…